245 lines
8.7 KiB
C
245 lines
8.7 KiB
C
/* $NetBSD: ka650.h,v 1.7 1999/08/07 10:36:46 ragge Exp $ */
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/*
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* Copyright (c) 1988 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Mt. Xinu.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ka650.h 7.5 (Berkeley) 6/28/90
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*/
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/*
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*
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* Definitions specific to the ka650 (uVAX 3600/3602) cpu card.
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*/
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/*
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* CAER: Memory System Error Register (IPR 39)
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*/
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#define CAER_DAL 0x00000040 /* CDAL or level 2 cache data parity */
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#define CAER_MCD 0x00000020 /* mcheck due to DAL parity error */
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#define CAER_MCC 0x00000010 /* mcheck due to 1st lev cache parity */
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#define CAER_DAT 0x00000002 /* data parity in 1st level cache */
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#define CAER_TAG 0x00000001 /* tag parity in 1st level cache */
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/*
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* CADR: Cache Disable Register (IPR 37)
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*/
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#define CADR_STMASK 0x000000f0 /* 1st level cache state mask */
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#define CADR_SEN2 0x00000080 /* 1st level cache set 2 enabled */
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#define CADR_SEN1 0x00000040 /* 1st level cache set 1 enabled */
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#define CADR_CENI 0x00000020 /* 1st level I-stream caching enabled */
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#define CADR_CEND 0x00000010 /* 1st level D-stream caching enabled */
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/*
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* Internal State Info 2: (for mcheck recovery)
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*/
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#define IS2_VCR 0x00008000 /* VAX Can't Restart flag */
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/*
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* DMA System Error Register (merr_dser)
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*/
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#define DSER_QNXM 0x00000080 /* Q-22 Bus NXM */
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#define DSER_QPE 0x00000020 /* Q-22 Bus parity Error */
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#define DSER_MEM 0x00000010 /* Main mem err due to ext dev DMA */
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#define DSER_LOST 0x00000008 /* Lost error: DSER <7,5,4,0> set */
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#define DSER_NOGRANT 0x00000004 /* No Grant timeout on cpu demand R/W */
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#define DSER_DNXM 0x00000001 /* DMA NXM */
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#define DSER_CLEAR (DSER_QNXM | DSER_QPE | DSER_MEM | \
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DSER_LOST | DSER_NOGRANT | DSER_DNXM)
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#define DMASER_BITS \
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"\20\20BHALT\17DCNEG\10QBNXM\6QBPE\5MEMERR\4LOSTERR\3NOGRANT\1DMANXM"
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#ifndef _LOCORE
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/*
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* Local registers (in I/O space)
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* This is done in disjoint sections. Map names are set in locore.s
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* and they are mapped in routine configcpu()
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*/
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/*
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* memory error & configuration registers
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*/
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struct ka650_merr {
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u_long merr_scr; /* System Config Register */
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u_long merr_dser; /* DMA System Error Register */
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u_long merr_qbear; /* QBus Error Address Register */
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u_long merr_dear; /* DMA Error Address Register */
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u_long merr_qbmbr; /* Q Bus Map Base address Register */
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u_long pad[59];
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u_long merr_csr[16]; /* Main Memory Config Regs (16 banks) */
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u_long merr_errstat; /* Main Memory Error Status */
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u_long merr_cont; /* Main Memory Control */
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};
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#define KA650_MERR 0x20080000
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/*
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* Main Memory Error Status Register (merr_errstat)
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*/
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#define MEM_EMASK 0xe0000180 /* mask of all err bits */
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#define MEM_RDS 0x80000000 /* uncorrectable main memory */
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#define MEM_RDSHIGH 0x40000000 /* high rate RDS errors */
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#define MEM_CRD 0x20000000 /* correctable main memory */
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#define MEM_DMA 0x00000100 /* DMA read or write error */
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#define MEM_CDAL 0x00000080 /* CDAL Parity error on write */
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#define MEM_PAGE 0x1ffffe00 /* Offending Page Number */
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#define MEM_PAGESHFT 9 /* Shift to normalize page number */
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/*
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* Main Memory Control & Diag Status Reg (merr_cont)
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*/
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#define MEM_CRDINT 0x00001000 /* CRD interrupts enabled */
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#define MEM_REFRESH 0x00000800 /* Forced memory refresh */
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#define MEM_ERRDIS 0x00000400 /* error detect disable */
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#define MEM_DIAG 0x00000080 /* Diagnostics mode */
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#define MEM_CHECK 0x0000007f /* check bits for diagnostic mode */
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/*
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* Main Memory Config Regs (merr_csr[0-15])
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*/
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#define MEM_BNKENBLE 0x80000000 /* Bank Enable */
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#define MEM_BNKNUM 0x03c00000 /* Physical map Bank number */
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#define MEM_BNKUSAGE 0x00000003 /* Bank Usage */
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/*
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* Cache Control & Boot/Diag registers
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*/
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struct ka650_cbd {
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u_char cbd_cacr; /* Low byte: Cache Enable & Parity Err detect */
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u_char cbd_cdf1; /* Cache diagnostic field (unused) */
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u_char cbd_cdf2; /* Cache diagnostic field (unused) */
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u_char pad;
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u_long cbd_bdr; /* Boot & Diagnostic Register (unused) */
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};
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#define KA650_CBD 0x20084000
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/*
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* CACR: Cache Control Register (2nd level cache) (cbd_cacr)
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*/
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#define CACR_CEN 0x00000010 /* Cache enable */
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#define CACR_CPE 0x00000020 /* Cache Parity Error */
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/*
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* System Support Chip (SSC) registers
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*/
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struct ka650_ssc {
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u_long ssc_sscbr; /* SSC Base Addr Register */
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u_long pad1[3];
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u_long ssc_ssccr; /* SSC Configuration Register */
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u_long pad2[3];
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u_long ssc_cbtcr; /* CDAL Bus Timeout Control Register */
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u_long pad3[55];
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u_long ssc_tcr0; /* timer control reg 0 */
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u_long ssc_tir0; /* timer interval reg 0 */
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u_long ssc_tnir0; /* timer next interval reg 0 */
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u_long ssc_tivr0; /* timer interrupt vector reg 0 */
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u_long ssc_tcr1; /* timer control reg 1 */
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u_long ssc_tir1; /* timer interval reg 1 */
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u_long ssc_tnir1; /* timer next interval reg 1 */
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u_long ssc_tivr1; /* timer interrupt vector reg 1 */
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u_long pad4[184];
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u_char ssc_cpmbx; /* Console Program Mail Box: Lang & Hact */
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u_char ssc_terminfo; /* TTY info: Video Dev, MCS, CRT & ROM flags */
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u_char ssc_keyboard; /* Keyboard code */
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};
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#define KA650_SSC 0x20140000
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/*
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* CBTCR: CDAL Bus Timeout Control Register (ssc_cbtcr)
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*/
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#define CBTCR_BTO 0x80000000 /* r/w unimp IPR or unack intr */
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#define CBTCR_RWT 0x40000000 /* CDAL Bus Timeout on CPU or DMA */
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/*
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* TCR0/TCR1: Programable Timer Control Registers (ssc_tcr[01])
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* (The rest of the bits are the same as in the standard VAX
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* Interval timer and are defined in clock.h)
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*/
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#define TCR_STP 0x00000004 /* Stop after time-out */
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/*
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* Flags for Console Program Mail Box
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*/
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#define CPMB650_HALTACT 0x03 /* Field for halt action */
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#define CPMB650_RESTART 0x01 /* Restart */
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#define CPMB650_REBOOT 0x02 /* Reboot */
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#define CPMB650_HALT 0x03 /* Halt */
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#define CPMB650_BIP 0x04 /* Bootstrap in progress */
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#define CPMB650_RIP 0x08 /* Restart in progress */
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#define CPMB650_DOTHIS 0x30 /* Execute sommand */
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#define CPMB650_LANG 0xf0 /* Language field */
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/*
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* Inter Processor Communication Register
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* To determine if memory error was from QBUS device DMA (as opposed to cpu).
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*/
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struct ka650_ipcr {
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u_long pad[80];
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u_short ipcr0; /* InterProcessor Comm Reg for arbiter */
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};
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#define KA650_IPCR 0x20001e00
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#endif _LOCORE
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/*
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* Physical start address of the Qbus memory.
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* The q-bus memory size is 4 meg.
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* Physical start address of the I/O space (where the 8Kbyte I/O page is).
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*/
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#define KA650_QMEM 0x30000000
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#define KA650_QMEMSIZE (512*8192)
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#define KA650_QDEVADDR 0x20000000
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/*
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* Mapping info for Cache Entries, including
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* Size (in bytes) of 2nd Level Cache for cache flush operation
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*/
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#define KA650_CACHE 0x10000000
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#define KA650_CACHESIZE (64*1024)
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/*
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* Useful ROM addresses
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*/
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#define KA650ROM_SIDEX 0x20060004 /* system ID extension */
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#define KA650ROM_GETC 0x20060008 /* (jsb) get character from console */
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#define KA650ROM_PUTS 0x2006000c /* (jsb) put string to console */
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#define KA650ROM_GETS 0x20060010 /* (jsb) read string with prompt */
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#define KA650_CONSTYPE 0x20140401 /* byte at which console type resides */
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/*
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* Some useful macros
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*/
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#define GETCPUTYPE(x) ((x >> 24) & 0xff)
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#define GETSYSSUBT(x) ((x >> 8) & 0xff)
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#define GETFRMREV(x) ((x >> 16) & 0xff)
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#define GETCODREV(x) (x & 0xff)
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