100 lines
3.9 KiB
C
100 lines
3.9 KiB
C
/* $NetBSD: ixp12x0_comreg.h,v 1.7 2003/03/06 06:14:16 igy Exp $ */
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/*
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* Copyright (c) 2002
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* Ichiro FUKUHARA <ichiro@ichiro.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS
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* HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* IXP12X0 UART register
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* UART_SR 0x90003400
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* UART_CR 0x90003800
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* UART_DR 0x90003C00
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*/
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#ifndef _IXP12X0_COMREG_H_
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#define _IXP12X0_COMREG_H_
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#define IXPCOM_FREQ (3686400 / 16)
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#define IXPCOMSPEED(b) (IXPCOM_FREQ / (b) - 1)
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#define IXPCOMSPEED2BRD(b) (IXPCOMSPEED(b) << 16)
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/* I/O space */
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#define IXPCOM_UART_SIZE 0x00004000UL
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#define IXPCOM_UART_OFFSET 0x00000000UL
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#define IXPCOM_UART_HWBASE (IXP12X0_SYS_HWBASE + IXPCOM_UART_OFFSET)
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/* IXPCOM_UART_VBASE should be used only for console's ioh. */
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#define IXPCOM_UART_VBASE (IXP12X0_SYS_VBASE + IXPCOM_UART_OFFSET)
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/* UART control register */
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#define IXPCOM_CR 0x00003800UL
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#define CR_BRK 0x01 /* Break */
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#define CR_PE 0x02 /* Parity enable */
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#define CR_OES 0x04 /* Odd/even parity select */
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#define CR_SBS 0x08 /* Stop bit select */
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#define SBS_1STOP (0 << 3) /* 1 Stop Bit */
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#define SBS_2STOP (1 << 3) /* 2 Stop Bit */
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#define CR_RIE 0x10 /* Receive FIFO interrupt enable */
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#define CR_DSS 0x60 /* Data size select */
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#define DSS_5BIT (0 << 5) /* 5Bits */
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#define DSS_6BIT (1 << 5) /* 6Bits */
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#define DSS_7BIT (2 << 5) /* 7Bits */
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#define DSS_8BIT (3 << 5) /* 8Bits */
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#define CR_UE 0x80 /* UART Enable */
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#define UE_DISABLE (0 << 7) /* UART Disabled */
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#define UE_ENABLE (1 << 7) /* UART Enabled */
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#define CR_XIE 0x100 /* Transmit FIFO interrupt enable */
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#define CR_UIS 0x200 /* UART Interrupt Select */
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#define CR_BRD 0x03ff0000 /* Baud rate divisor */
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/* UART Status register */
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#define IXPCOM_SR 0x00003400UL
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#define SR_PRE 0x01 /* Parity error */
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#define SR_FRE 0x02 /* Framing error */
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#define SR_TXR 0x04 /* Transmit FIFO Ready */
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#define SR_ROR 0x08 /* Receiver overrun */
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#define SR_RXR 0x10 /* Receiver FIFO Ready */
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#define SR_TXE 0x20 /* Transmit FIFO Empty */
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#define SR_RXF 0x40 /* Receiver FIFO Full */
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#define SR_TXF 0x80 /* Transmit FIFO Full */
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/* UART data register */
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#define IXPCOM_DR 0x00003C00UL
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#define DR_PRE 0x100 /* Parity error */
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#define DR_FRE 0x200 /* Framing error */
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#define DR_ROR 0x400 /* Receiver overrun */
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#define IXPCOMSPLRAISED (~(CR_RIE | CR_XIE))
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#define IXPCOMSPLLOWERD (~0UL);
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#endif /* _IXP12X0_COMREG_H_ */
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