f0d6660cf4
Renamed in sys/dev/ic: i4b_hscx.c -> hscx.c i4b_hscx.h -> hscx.h i4b_ipac.h -> ipac.h i4b_isac.c -> isac.c i4b_isac.h -> isac.h i4b_isic.c -> isic.c i4b_isicbchan.c -> isic_bchan.c i4b_isicl1.c -> isic_l1.c i4b_isicl1.h -> isic_l1.h i4b_isicl1fsm.c -> isic_l1fsm.c
502 lines
14 KiB
C
502 lines
14 KiB
C
/*
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* Copyright (c) 1997, 1999 Hellmuth Michaelis. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* isic - I4B Siemens ISDN Chipset Driver for ELSA Quickstep 1000pro ISA
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* =====================================================================
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*
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* $Id: isic_isapnp_elsa_qs1i.c,v 1.2 2001/02/20 22:24:39 martin Exp $
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*
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* last edit-date: [Fri Jan 5 11:38:29 2001]
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*
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*---------------------------------------------------------------------------*/
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#include "opt_isicpnp.h"
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#if defined(ISICPNP_ELSA_QS1ISA) || defined(ISICPNP_ELSA_PCC16)
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#if defined(__NetBSD__) && __NetBSD_Version__ >= 104230000
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#include <sys/callout.h>
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#endif
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#ifdef __FreeBSD__
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#if __FreeBSD__ >= 3
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#include <sys/ioccom.h>
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#else
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#include <sys/ioctl.h>
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#endif
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#include <machine/clock.h>
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#include <i386/isa/isa_device.h>
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#include <i386/isa/pnp.h>
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#else
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#include <machine/bus.h>
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#include <sys/device.h>
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#endif
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#ifdef __FreeBSD__
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#include <machine/i4b_debug.h>
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#include <machine/i4b_ioctl.h>
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#else
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#include <netisdn/i4b_debug.h>
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#include <netisdn/i4b_ioctl.h>
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#endif
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#include <netisdn/i4b_global.h>
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#include <netisdn/i4b_l1l2.h>
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#include <netisdn/i4b_mbuf.h>
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#include <dev/ic/isic_l1.h>
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#include <dev/ic/isac.h>
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#include <dev/ic/hscx.h>
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#ifdef __FreeBSD__
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static void i4b_eq1i_clrirq(void* base);
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#else
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static void i4b_eq1i_clrirq(struct l1_softc *sc);
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void isic_attach_Eqs1pi __P((struct l1_softc *sc));
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#endif
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/* masks for register encoded in base addr */
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#define ELSA_BASE_MASK 0x0ffff
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#define ELSA_OFF_MASK 0xf0000
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/* register id's to be encoded in base addr */
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#define ELSA_IDISAC 0x00000
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#define ELSA_IDHSCXA 0x10000
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#define ELSA_IDHSCXB 0x20000
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/* offsets from base address */
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#define ELSA_OFF_ISAC 0x00
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#define ELSA_OFF_HSCX 0x02
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#define ELSA_OFF_OFF 0x03
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#define ELSA_OFF_CTRL 0x04
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#define ELSA_OFF_CFG 0x05
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#define ELSA_OFF_TIMR 0x06
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#define ELSA_OFF_IRQ 0x07
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/* control register (write access) */
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#define ELSA_CTRL_LED_YELLOW 0x02
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#define ELSA_CTRL_LED_GREEN 0x08
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#define ELSA_CTRL_RESET 0x20
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#define ELSA_CTRL_TIMEREN 0x80
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#define ELSA_CTRL_SECRET 0x50
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/*---------------------------------------------------------------------------*
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* ELSA QuickStep 1000pro/ISA clear IRQ routine
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*---------------------------------------------------------------------------*/
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#ifdef __FreeBSD__
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static void
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i4b_eq1i_clrirq(void* base)
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{
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outb((u_int)base + ELSA_OFF_IRQ, 0);
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}
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#else
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static void
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i4b_eq1i_clrirq(struct l1_softc *sc)
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{
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bus_space_tag_t t = sc->sc_maps[0].t;
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bus_space_handle_t h = sc->sc_maps[0].h;
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bus_space_write_1(t, h, ELSA_OFF_IRQ, 0);
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}
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#endif
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/*---------------------------------------------------------------------------*
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* ELSA QuickStep 1000pro/ISA ISAC get fifo routine
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*---------------------------------------------------------------------------*/
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#ifdef __FreeBSD__
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static void
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eqs1pi_read_fifo(void *buf, const void *base, size_t len)
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{
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if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDHSCXB)
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{
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outb((u_int)((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, 0x40);
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insb((((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_HSCX), (u_char *)buf, (u_int)len);
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}
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else if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDHSCXA)
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{
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outb((u_int)((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, 0);
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insb((((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_HSCX), (u_char *)buf, (u_int)len);
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}
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else /* if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDISAC) */
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{
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outb((u_int)((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, 0);
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insb((((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_ISAC), (u_char *)buf, (u_int)len);
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}
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}
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#else
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static void
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eqs1pi_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
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{
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bus_space_tag_t t = sc->sc_maps[0].t;
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bus_space_handle_t h = sc->sc_maps[0].h;
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switch (what) {
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t, h, ELSA_OFF_OFF, 0);
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bus_space_read_multi_1(t, h, ELSA_OFF_ISAC, buf, size);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t, h, ELSA_OFF_OFF, 0);
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bus_space_read_multi_1(t, h, ELSA_OFF_HSCX, buf, size);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t, h, ELSA_OFF_OFF, 0x40);
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bus_space_read_multi_1(t, h, ELSA_OFF_HSCX, buf, size);
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break;
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}
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}
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#endif
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/*---------------------------------------------------------------------------*
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* ELSA QuickStep 1000pro/ISA ISAC put fifo routine
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*---------------------------------------------------------------------------*/
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#ifdef __FreeBSD__
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static void
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eqs1pi_write_fifo(void *base, const void *buf, size_t len)
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{
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if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDHSCXB)
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{
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outb((u_int)((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, 0x40);
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outsb((((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_HSCX), (u_char *)buf, (u_int)len);
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}
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else if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDHSCXA)
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{
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outb((u_int)((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, 0);
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outsb((((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_HSCX), (u_char *)buf, (u_int)len);
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}
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else /* if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDISAC) */
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{
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outb((u_int)((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, 0);
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outsb((((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_ISAC), (u_char *)buf, (u_int)len);
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}
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}
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#else
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static void
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eqs1pi_write_fifo(struct l1_softc *sc, int what, const void *buf, size_t size)
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{
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bus_space_tag_t t = sc->sc_maps[0].t;
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bus_space_handle_t h = sc->sc_maps[0].h;
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switch (what) {
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t, h, ELSA_OFF_OFF, 0);
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bus_space_write_multi_1(t, h, ELSA_OFF_ISAC, (u_int8_t*)buf, size);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t, h, ELSA_OFF_OFF, 0);
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bus_space_write_multi_1(t, h, ELSA_OFF_HSCX, (u_int8_t*)buf, size);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t, h, ELSA_OFF_OFF, 0x40);
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bus_space_write_multi_1(t, h, ELSA_OFF_HSCX, (u_int8_t*)buf, size);
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break;
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}
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}
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#endif
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/*---------------------------------------------------------------------------*
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* ELSA QuickStep 1000pro/ISA ISAC put register routine
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*---------------------------------------------------------------------------*/
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#ifdef __FreeBSD__
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static void
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eqs1pi_write_reg(u_char *base, u_int offset, u_int v)
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{
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if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDHSCXB)
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{
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outb(((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, (u_char)(offset+0x40));
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outb(((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_HSCX, (u_char)v);
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}
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else if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDHSCXA)
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{
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outb(((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, (u_char)offset);
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outb(((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_HSCX, (u_char)v);
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}
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else /* if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDISAC) */
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{
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outb(((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, (u_char)offset);
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outb(((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_ISAC, (u_char)v);
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}
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}
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#else
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static void
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eqs1pi_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
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{
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bus_space_tag_t t = sc->sc_maps[0].t;
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bus_space_handle_t h = sc->sc_maps[0].h;
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switch (what) {
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t, h, ELSA_OFF_OFF, offs);
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bus_space_write_1(t, h, ELSA_OFF_ISAC, data);
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break;
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t, h, ELSA_OFF_OFF, offs);
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bus_space_write_1(t, h, ELSA_OFF_HSCX, data);
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break;
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t, h, ELSA_OFF_OFF, 0x40+offs);
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bus_space_write_1(t, h, ELSA_OFF_HSCX, data);
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break;
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}
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}
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#endif
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/*---------------------------------------------------------------------------*
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* ELSA QuickStep 1000pro/ISA ISAC get register routine
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*---------------------------------------------------------------------------*/
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#ifdef __FreeBSD__
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static u_char
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eqs1pi_read_reg(u_char *base, u_int offset)
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{
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if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDHSCXB)
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{
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outb((u_int)((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, (u_char)(offset+0x40));
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return(inb(((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_HSCX));
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}
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else if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDHSCXA)
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{
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outb((u_int)((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, (u_char)offset);
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return(inb(((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_HSCX));
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}
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else /* if(((u_int)base & ELSA_OFF_MASK) == ELSA_IDISAC) */
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{
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outb((u_int)((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_OFF, (u_char)offset);
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return(inb(((u_int)base & ELSA_BASE_MASK) + ELSA_OFF_ISAC));
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}
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}
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#else
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static u_int8_t
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eqs1pi_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
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{
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bus_space_tag_t t = sc->sc_maps[0].t;
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bus_space_handle_t h = sc->sc_maps[0].h;
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switch (what) {
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case ISIC_WHAT_ISAC:
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bus_space_write_1(t, h, ELSA_OFF_OFF, offs);
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return bus_space_read_1(t, h, ELSA_OFF_ISAC);
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case ISIC_WHAT_HSCXA:
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bus_space_write_1(t, h, ELSA_OFF_OFF, offs);
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return bus_space_read_1(t, h, ELSA_OFF_HSCX);
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case ISIC_WHAT_HSCXB:
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bus_space_write_1(t, h, ELSA_OFF_OFF, 0x40+offs);
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return bus_space_read_1(t, h, ELSA_OFF_HSCX);
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}
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return 0;
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}
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#endif
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#ifdef __FreeBSD__
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/*---------------------------------------------------------------------------*
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* isic_probe_Eqs1pi - probe for ELSA QuickStep 1000pro/ISA and compatibles
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*---------------------------------------------------------------------------*/
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int
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isic_probe_Eqs1pi(struct isa_device *dev, unsigned int iobase2)
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{
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struct l1_softc *sc = &l1_sc[dev->id_unit];
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/* check max unit range */
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if(dev->id_unit >= ISIC_MAXUNIT)
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{
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printf("isic%d: Error, unit %d >= ISIC_MAXUNIT for ELSA QuickStep 1000pro/ISA!\n",
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dev->id_unit, dev->id_unit);
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return(0);
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}
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sc->sc_unit = dev->id_unit;
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/* check IRQ validity */
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switch(ffs(dev->id_irq) - 1)
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{
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case 3:
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case 4:
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case 5:
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case 7:
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case 10:
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case 11:
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case 12:
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case 15:
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break;
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default:
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printf("isic%d: Error, invalid IRQ [%d] specified for ELSA QuickStep 1000pro/ISA!\n",
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dev->id_unit, ffs(dev->id_irq)-1);
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return(0);
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break;
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}
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sc->sc_irq = dev->id_irq;
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/* check if memory addr specified */
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if(dev->id_maddr)
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{
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printf("isic%d: Error, mem addr 0x%lx specified for ELSA QuickStep 1000pro/ISA!\n",
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dev->id_unit, (u_long)dev->id_maddr);
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return(0);
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}
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dev->id_msize = 0;
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/* check if we got an iobase */
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if(!((dev->id_iobase >= 0x160) && (dev->id_iobase <= 0x360)))
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{
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printf("isic%d: Error, invalid iobase 0x%x specified for ELSA QuickStep 1000pro/ISA!\n",
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dev->id_unit, dev->id_iobase);
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return(0);
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}
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sc->sc_port = dev->id_iobase;
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/* setup access routines */
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sc->clearirq = i4b_eq1i_clrirq;
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sc->readreg = eqs1pi_read_reg;
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sc->writereg = eqs1pi_write_reg;
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sc->readfifo = eqs1pi_read_fifo;
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sc->writefifo = eqs1pi_write_fifo;
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/* setup card type */
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sc->sc_cardtyp = CARD_TYPEP_ELSAQS1ISA;
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/* setup IOM bus type */
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sc->sc_bustyp = BUS_TYPE_IOM2;
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sc->sc_ipac = 0;
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sc->sc_bfifolen = HSCX_FIFO_LEN;
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/* setup ISAC and HSCX base addr */
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ISAC_BASE = (caddr_t) ((u_int)dev->id_iobase | ELSA_IDISAC);
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HSCX_A_BASE = (caddr_t) ((u_int)dev->id_iobase | ELSA_IDHSCXA);
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HSCX_B_BASE = (caddr_t) ((u_int)dev->id_iobase | ELSA_IDHSCXB);
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/*
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* Read HSCX A/B VSTR. Expected value for the ELSA QuickStep 1000pro
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* ISA card is 0x05 ( = version 2.1 ) in the least significant bits.
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*/
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if( ((HSCX_READ(0, H_VSTR) & 0xf) != 0x5) ||
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((HSCX_READ(1, H_VSTR) & 0xf) != 0x5) )
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{
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printf("isic%d: HSCX VSTR test failed for ELSA QuickStep 1000pro/ISA\n",
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dev->id_unit);
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printf("isic%d: HSC0: VSTR: %#x\n",
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dev->id_unit, HSCX_READ(0, H_VSTR));
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printf("isic%d: HSC1: VSTR: %#x\n",
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dev->id_unit, HSCX_READ(1, H_VSTR));
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return (0);
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}
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return (1);
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}
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|
|
|
/*---------------------------------------------------------------------------*
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|
* isic_attach_s0163P - attach ELSA QuickStep 1000pro/ISA
|
|
*---------------------------------------------------------------------------*/
|
|
int
|
|
isic_attach_Eqs1pi(struct isa_device *dev, unsigned int iobase2)
|
|
{
|
|
u_char byte = ELSA_CTRL_SECRET;
|
|
|
|
byte &= ~ELSA_CTRL_RESET;
|
|
outb(dev->id_iobase + ELSA_OFF_CTRL, byte);
|
|
DELAY(20);
|
|
byte |= ELSA_CTRL_RESET;
|
|
outb(dev->id_iobase + ELSA_OFF_CTRL, byte);
|
|
|
|
DELAY(20);
|
|
outb(dev->id_iobase + ELSA_OFF_IRQ, 0xff);
|
|
|
|
return(1);
|
|
}
|
|
|
|
#else /* !__FreeBSD__ */
|
|
|
|
void
|
|
isic_attach_Eqs1pi(struct l1_softc *sc)
|
|
{
|
|
bus_space_tag_t t = sc->sc_maps[0].t;
|
|
bus_space_handle_t h = sc->sc_maps[0].h;
|
|
u_char byte = ELSA_CTRL_SECRET;
|
|
|
|
byte &= ~ELSA_CTRL_RESET;
|
|
bus_space_write_1(t, h, ELSA_OFF_CTRL, byte);
|
|
DELAY(20);
|
|
byte |= ELSA_CTRL_RESET;
|
|
bus_space_write_1(t, h, ELSA_OFF_CTRL, byte);
|
|
|
|
DELAY(20);
|
|
bus_space_write_1(t, h, ELSA_OFF_IRQ, 0xff);
|
|
|
|
/* setup access routines */
|
|
|
|
sc->clearirq = i4b_eq1i_clrirq;
|
|
sc->readreg = eqs1pi_read_reg;
|
|
sc->writereg = eqs1pi_write_reg;
|
|
|
|
sc->readfifo = eqs1pi_read_fifo;
|
|
sc->writefifo = eqs1pi_write_fifo;
|
|
|
|
/* setup card type */
|
|
|
|
sc->sc_cardtyp = CARD_TYPEP_ELSAQS1ISA;
|
|
|
|
/* setup IOM bus type */
|
|
|
|
sc->sc_bustyp = BUS_TYPE_IOM2;
|
|
|
|
sc->sc_ipac = 0;
|
|
sc->sc_bfifolen = HSCX_FIFO_LEN;
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* ISICPNP_ELSA_QS1ISA or ISICPNP_ELSA_PCC16 */
|