2bf916e97d
sequence using the reciprocal of the delay divisor to perform the division. Set the cp0 compare register so that it doesn't trigger interrupts and reset the cp0 count register in the hardclock interrupt handler. |
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| .. | ||
| sbgbus.c | ||
| sbgbusvar.h | ||
| sbjcn.c | ||
| sbjcnvar.h | ||
| sbmac.c | ||
| sbobio.c | ||
| sbobiovar.h | ||
| sbscd.c | ||
| sbscdvar.h | ||
| sbscn.c | ||
| sbscnvar.h | ||
| sbtimer.c | ||