144 lines
5.0 KiB
C
144 lines
5.0 KiB
C
/* $NetBSD: plumicureg.h,v 1.3 2001/09/15 12:47:06 uch Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PLUM2 INTERRUPT CONTROLLER UNIT
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*/
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#define PLUM_INT_REGBASE 0x8000
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#define PLUM_INT_REGSIZE 0x1000
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/*
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* Interrupt status register
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*/
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#define PLUM_INT_INTSTA_REG 0x000
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#define PLUM_INT_INTSTA_EXTINT 0x00000080
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#define PLUM_INT_INTSTA_SMINT 0x00000040
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#define PLUM_INT_INTSTA_USBWAKE 0x00000020
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#define PLUM_INT_INTSTA_USBINT 0x00000010
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#define PLUM_INT_INTSTA_DISPINT 0x00000008
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#define PLUM_INT_INTSTA_C2SCINT 0x00000004
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#define PLUM_INT_INTSTA_C1SCINT 0x00000002
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#define PLUM_INT_INTSTA_PCCINT 0x00000001
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/*
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* Interrupt enable register
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*/
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#define PLUM_INT_INTIEN_REG 0x010
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#define PLUM_INT_INTIEN 0x00000001
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/*
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* External interrupts
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*/
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/* outside input interrupt status register */
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#define PLUM_INT_EXTINTS_REG 0x100
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#define PLUM_INT_EXTINTS_IO3INT1 0x00000020
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#define PLUM_INT_EXTINTS_IO3INT0 0x00000010
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#define PLUM_INT_EXTINTS_IO5INT3 0x00000008
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#define PLUM_INT_EXTINTS_IO5INT2 0x00000004
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#define PLUM_INT_EXTINTS_IO5INT1 0x00000002
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#define PLUM_INT_EXTINTS_IO5INT0 0x00000001
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/* outside input interrupt status register (after the mask) */
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#define PLUM_INT_EXTINTM_REG 0x104
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/* interrupt enable register from the outside input */
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#define PLUM_INT_EXTIEN_REG 0x110
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#define PLUM_INT_EXTIEN_IENIO3INT1 0x00000020
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#define PLUM_INT_EXTIEN_IENIO3INT0 0x00000010
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#define PLUM_INT_EXTIEN_IENIO5INT3 0x00000008
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#define PLUM_INT_EXTIEN_IENIO5INT2 0x00000004
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#define PLUM_INT_EXTIEN_IENIO5INT1 0x00000002
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#define PLUM_INT_EXTIEN_IENIO5INT0 0x00000001
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#define PLUM_INT_EXTIEN_SENIO3INT1 0x00002000
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#define PLUM_INT_EXTIEN_SENIO3INT0 0x00001000
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#define PLUM_INT_EXTIEN_SENIO5INT3 0x00000800
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#define PLUM_INT_EXTIEN_SENIO5INT2 0x00000400
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#define PLUM_INT_EXTIEN_SENIO5INT1 0x00000200
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#define PLUM_INT_EXTIEN_SENIO5INT0 0x00000100
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/*
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* PC-card interrupts
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*/
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/* PC-card interrupt status register */
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#define PLUM_INT_PCCINTS_REG 0x200
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#define PLUM_INT_PCCINTS_C2RI 0x00000008
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#define PLUM_INT_PCCINTS_C2IO 0x00000004
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#define PLUM_INT_PCCINTS_C1RI 0x00000002
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#define PLUM_INT_PCCINTS_C1IO 0x00000001
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/* PC-card interrupt status register (masked) */
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#define PLUM_INT_PCCINTM_REG 0x204
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/* PC-card interrupt enable register */
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#define PLUM_INT_PCCIEN_REG 0x210
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#define PLUM_INT_PCCIEN_SENC2RI 0x00000800
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#define PLUM_INT_PCCIEN_SENC2IO 0x00000400
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#define PLUM_INT_PCCIEN_SENC1RI 0x00000200
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#define PLUM_INT_PCCIEN_SENC1IO 0x00000100
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#define PLUM_INT_PCCIEN_IENC2RI 0x00000008
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#define PLUM_INT_PCCIEN_IENC2IO 0x00000004
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#define PLUM_INT_PCCIEN_IENC1RI 0x00000002
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#define PLUM_INT_PCCIEN_IENC1IO 0x00000001
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/* PC-card interrupt detection register */
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#define PLUM_INT_PCCLKSL_REG 0x220
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#define PLUM_INT_PCCLKSL_RTC 0x00000001 /*(for suspend mode)*/
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/*
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* USB interrupts
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*/
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/* USB interrupt enable register */
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#define PLUM_INT_USBINTEN_REG 0x310
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/* master-enables the USB interrupts */
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#define PLUM_INT_USBINTEN_IEN 0x00000002
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/* enbales the clock restart request interrupts */
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#define PLUM_INT_USBINTEN_WIEN 0x00000001
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/*
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* SmartMedia interrupts
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*/
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/* SmartMedia interrupt enable register */
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#define PLUM_INT_SMIEN_REG 0x410
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#define PLUM_INT_SMIEN 0x00000001
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