215 lines
6.8 KiB
Groff
215 lines
6.8 KiB
Groff
.\" $NetBSD: ioasic.9,v 1.13 2017/07/03 21:28:48 wiz Exp $
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.\"
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.\" Copyright (c) 2000 The NetBSD Foundation, Inc.
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.\" All rights reserved.
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.\"
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.\" This code is derived from software contributed to The NetBSD Foundation
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.\" by Gregory McGarry.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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.\" POSSIBILITY OF SUCH DAMAGE.
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.\"
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.Dd August 6, 2000
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.Dt IOASIC 9
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.Os
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.Sh NAME
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.Nm IOASIC ,
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.Nm ioasic_intr_establish ,
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.Nm ioasic_intr_disestablish ,
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.Nm ioasic_intr_evcnt ,
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.Nm ioasic_attach_devs ,
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.Nm ioasic_submatch
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.Nd baseboard I/O control ASIC for DEC TURBOchannel systems
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.Sh SYNOPSIS
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.In sys/bus.h
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.In dev/tc/tcvar.h
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.In dev/tc/ioasicreg.h
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.In dev/tc/ioasicvar.h
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.Ft void
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.Fn ioasic_intr_establish "struct device *dev" "void *cookie" "int level" \
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"int (*handler)(void *)" "void *arg"
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.Ft void
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.Fn ioasic_intr_disestablish "struct device *dev" "void *cookie"
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.Ft const struct evcnt *
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.Fn ioasic_intr_evcnt "struct device *dev" "void *cookie"
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.Ft void
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.Fn ioasic_attach_devs "struct ioasic_softc *sc" \
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"struct ioasic_dev *ioasic_devs" "int ioasic_ndevs"
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.Ft int
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.Fn ioasic_submatch "struct cfdata *match" "struct ioasicdev_attach_args *ia"
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.Sh DESCRIPTION
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The
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.Nm
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device provides support for the DEC proprietary IOCTL ASIC found on
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all DEC TURBOchannel machines with MIPS (DECstation 5000 series,
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excluding the 5000/200) and Alpha (3000-series) systems.
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The
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.Nm
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is memory-mapped into the TURBOchannel system slot to interface up to
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sixteen I/O devices.
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It connects the TURBOchannel to a 16-bit wide I/O bus and supplies
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various control signals to the devices that share this bus.
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.Pp
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The
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.Nm
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provides hardware DMA channels and interrupt support.
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DMA transfers are between one and four 32-bit words (16 bytes) in
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length, depending on the device.
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The
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.Nm
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stores the data in internal data registers.
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The data is transferred to and from the registers in 16-bit words
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to the device.
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Various interrupts are signalled on DMA pointer-related conditions.
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.Sh DATA TYPES
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Drivers for devices attached to the
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.Nm
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will make use of the following data types:
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.Bl -tag -width compact
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.It Fa struct ioasicdev_attach_args
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A structure used to inform the driver of the
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.Nm
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device properties.
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It contains the following members:
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.Bd -literal
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char iada_modname
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tc_offset_t iada_offset
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tc_addr_t iada_addr
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void *iada_cookie;
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.Ed
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.It Fa struct ioasic_softc
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The parent structure which contains at the following members which are
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useful for drivers:
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.Bd -literal
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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bus_dma_tag_t sc_dmat;
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.Ed
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.It Fa struct ioasic_dev
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A structure describing the machine-dependent devices attached to the
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.Nm
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containing the following members:
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.Bd -literal
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char *iad_modname;
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tc_offset_t iad_offset;
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void *iad_cookie;
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uint32_t iad_intrbits;
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.Ed
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.El
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.Sh FUNCTIONS
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.Bl -tag -width compact
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.It Fn ioasic_intr_establish "dev" "cookie" "level" "handler" "arg"
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Establish an interrupt handler with device
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.Fa dev
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for the interrupt described completely by
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.Fa cookie .
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The priority of the interrupt is specified by
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.Fa level .
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When the interrupt occurs the function
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.Fa handler
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is called with argument
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.Fa arg .
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.It Fn ioasic_intr_disestablish "dev" "cookie"
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Dis-establish the interrupt handler with device
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.Fa dev
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for the interrupt described complete ly
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.Fa cookie .
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.It Fn ioasic_intr_evcnt "dev" "cookie"
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Do interrupt event counting with device
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.Fa dev
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for the event described completely by
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.Fa cookie .
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.It Fn ioasic_attach_devs "sc" "ioasic_devs" "ioasic_ndevs"
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Configure each of the
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.Fa ioasic_ndevs
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devices in
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.Fa ioasic_devs .
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.It Fn ioasic_submatch "match" "ia"
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Check that the device offset is not OASIC_OFFSET_UNKNOWN.
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.El
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.Pp
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The
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.Fn ioasic_intr_establish ,
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.Fn ioasic_intr_disestablish ,
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and
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.Fn ioasic_intr_evcnt
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functions are likely to used by all
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.Nm
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device drivers.
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The
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.Fn ioasic_attach_devs
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function is used by ioasic driver internally and is of interest to
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driver writers because it must be aware of your device for it to be
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found during autoconfiguration.
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.Sh AUTOCONFIGURATION
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The IOASIC is a direct-connection bus.
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During autoconfiguration, machine-dependent code will provide an array of
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.Fa struct ioasic_devs
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describing devices attached to the
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.Nm
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to be used by the ioasic driver.
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The ioasic driver will pass this array to
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.Fn ioasic_attach_devs
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to attach the drivers with the devices.
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.Pp
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Drivers match the device using
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.Fa iada_modname .
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.Pp
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During attach, all drivers should use the parent's bus_space and
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bus_dma resources, and map the appropriate bus_space region using
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.Fn bus_space_subregion
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with
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.Fa iada_offset .
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.Sh DMA SUPPORT
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No additional support is provided for
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.Nm
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DMA beyond the facilities provided by the
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.Xr bus_dma 9
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interface.
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.Pp
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The
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.Nm
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provides two pairs of DMA address pointers (transmitting and
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receiving) for each DMA-capable device.
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The pair of address pointers point to consecutive (but not necessarily
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contiguous) DMA blocks of size IOASIC_DMA_BLOCKSIZE.
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Upon successful transfer of the first block, DMA continues to the next
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block and an interrupt is posted to signal an address pointer update.
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DMA transfers are enabled and disabled by bits inside the
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.Nm
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status (CSR) register.
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.Pp
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The interrupt handler must update the address pointers to point to the
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next block in the DMA transfer.
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The address pointer update must be completed before the completion of
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the second DMA block, otherwise a DMA overrun error condition will occur.
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.Sh CODE REFERENCES
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The IOASIC subsystem itself is implemented within the file
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.Pa sys/dev/tc/ioasic_subr.c .
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Machine-dependent portions can be found in
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.Pa sys/arch/<arch>/tc/ioasic.c .
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.Sh SEE ALSO
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.Xr ioasic 4 ,
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.Xr autoconf 9 ,
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.Xr bus_dma 9 ,
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.Xr bus_space 9 ,
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.Xr driver 9
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