d49c71cb8a
segments. - Use a much more obvious DMA job queueing scheme. - Fixup some debugging code.
137 lines
4.6 KiB
C
137 lines
4.6 KiB
C
/* $NetBSD: dmareg.h,v 1.8 1997/01/30 09:04:34 thorpej Exp $ */
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/*
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* Copyright (c) 1982, 1990, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)dmareg.h 8.1 (Berkeley) 6/10/93
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*/
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#include <hp300/dev/iotypes.h> /* XXX */
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/*
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* Hardware layout for the 98620[ABC]:
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* 98620A (old 320s?): byte/word DMA in up to 64K chunks
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* 98620B (320s only): 98620A with programmable IPL
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* 98620C (all others): byte/word/longword DMA in up to 4Gb chunks
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*/
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struct dmaBdevice {
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v_char *dmaB_addr;
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vu_short dmaB_count;
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vu_short dmaB_cmd;
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#define dmaB_stat dmaB_cmd
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};
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struct dmadevice {
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v_char *dma_addr;
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vu_int dma_count;
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vu_short dma_cmd;
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vu_short dma_stat;
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};
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struct dmareg {
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struct dmaBdevice dma_Bchan0;
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struct dmaBdevice dma_Bchan1;
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/* the rest are 98620C specific */
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v_char dma_id[4];
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vu_char dma_cr;
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char dma_pad1[0xEB];
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struct dmadevice dma_chan0;
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char dma_pad2[0xF4];
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struct dmadevice dma_chan1;
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};
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/* The hp300 has 2 DMA channels. */
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#define NDMACHAN 2
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/* addresses */
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#define DMA_BASE IIOV(0x500000)
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/* command bits */
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#define DMA_ENAB 0x0001
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#define DMA_WORD 0x0002
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#define DMA_WRT 0x0004
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#define DMA_PRI 0x0008
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#define DMA_IPL(x) (((x) - 3) << 4)
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#define DMA_LWORD 0x0100
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#define DMA_START 0x8000
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/* status bits */
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#define DMA_ARMED 0x01
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#define DMA_INTR 0x02
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#define DMA_ACC 0x04
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#define DMA_HALT 0x08
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#define DMA_BERR 0x10
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#define DMA_ALIGN 0x20
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#define DMA_WRAP 0x40
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#ifdef _KERNEL
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/*
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* Macros to attempt to hide the HW differences between the 98620B DMA
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* board and the 1TQ4-0401 DMA chip (68020C "board"). The latter
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* includes emulation registers for the former but you need to access
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* the "native-mode" registers directly in order to do 32-bit DMA.
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*
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* DMA_CLEAR: Clear interrupt on DMA board. We just use the
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* emulation registers on the 98620C as that is easiest.
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* DMA_STAT: Read status register. Again, we always read the
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* emulation register. Someday we might want to
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* look at the 98620C status to get the extended bits.
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* DMA_ARM: Load address, count and kick-off DMA.
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*/
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#define DMA_CLEAR(dc) { v_int dmaclr = (int) dc->dm_Bhwaddr->dmaB_addr; }
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#define DMA_STAT(dc) dc->dm_Bhwaddr->dmaB_stat
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#if defined(HP320)
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#define DMA_ARM(dc) \
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if (dc->dm_softc->sc_type == DMA_B) { \
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register struct dmaBdevice *dma = dc->dm_Bhwaddr; \
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dma->dmaB_addr = dc->dm_chain[dc->dm_cur].dc_addr; \
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dma->dmaB_count = dc->dm_chain[dc->dm_cur].dc_count - 1; \
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dma->dmaB_cmd = dc->dm_cmd; \
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} else { \
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register struct dmadevice *dma = dc->dm_hwaddr; \
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dma->dma_addr = dc->dm_chain[dc->dm_cur].dc_addr; \
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dma->dma_count = dc->dm_chain[dc->dm_cur].dc_count - 1; \
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dma->dma_cmd = dc->dm_cmd; \
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}
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#else
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#define DMA_ARM(dc) \
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{ \
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register struct dmadevice *dma = dc->dm_hwaddr; \
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dma->dma_addr = dc->dm_chain[dc->dm_cur].dc_addr; \
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dma->dma_count = dc->dm_chain[dc->dm_cur].dc_count - 1; \
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dma->dma_cmd = dc->dm_cmd; \
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}
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#endif
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#endif
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