493 lines
17 KiB
C
493 lines
17 KiB
C
/* $NetBSD: smc83c170reg.h,v 1.2 1998/07/20 20:45:06 thorpej Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_IC_SMC83C170REG_H_
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#define _DEV_IC_SMC83C170REG_H_
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/*
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* Register description for the Standard Microsystems Corp. 83C170
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* Ethernet PCI Integrated Controller (EPIC/100).
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*/
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/*
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* EPIC transmit descriptor. Must be 4-byte aligned.
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*/
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struct epic_txdesc {
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#if BYTE_ORDER == BIG_ENDIAN
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u_int16_t et_txlength; /* transmit length */
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u_int16_t et_txstatus; /* transmit status; see below */
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#else
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u_int16_t et_txstatus; /* transmit status; see below */
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u_int16_t et_txlength; /* transmit length */
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#endif
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u_int32_t et_bufaddr; /* buffer address */
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#if BYTE_ORDER == BIG_ENDIAN
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u_int16_t et_control; /* control word; see below */
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u_int16_t et_buflength; /* buffer length */
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#else
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u_int16_t et_buflength; /* buffer length */
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u_int16_t et_control; /* control word; see below */
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#endif
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u_int32_t et_nextdesc; /* next descriptor pointer */
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};
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/* et_txstatus */
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#define ET_TXSTAT_OWNER 0x8000 /* NIC owns descriptor */
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#define ET_TXSTAT_COLLMASK 0x1f00 /* collisions */
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#define ET_TXSTAT_DEFERRING 0x0080 /* deferring due to jabber */
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#define ET_TXSTAT_OOWCOLL 0x0040 /* out of window collision */
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#define ET_TXSTAT_CDHB 0x0020 /* collision detect heartbeat */
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#define ET_TXSTAT_UNDERRUN 0x0010 /* DMA underrun */
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#define ET_TXSTAT_CARSENSELOST 0x0008 /* carrier lost */
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#define ET_TXSTAT_TXWITHCOLL 0x0004 /* encountered collisions during tx */
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#define ET_TXSTAT_NONDEFERRED 0x0002 /* transmitted without deferring */
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#define ET_TXSTAT_PACKETTX 0x0001 /* packet transmitted successfully */
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#define TXSTAT_COLLISIONS(x) (((x) & ET_TXSTAT_COLLMASK) >> 8)
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/* et_control */
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#define ET_TXCTL_LASTDESC 0x0010 /* last descriptor in frame */
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#define ET_TXCTL_NOCRC 0x0008 /* disable CRC generation */
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#define ET_TXCTL_IAF 0x0004 /* interrupt after frame */
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#define ET_TXCTL_LFFORM 0x0002 /* alternate fraglist format */
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#define ET_TXCTL_FRAGLIST 0x0001 /* descriptor points to fraglist */
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/*
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* EPIC receive descriptor. Must be 4-byte aligned.
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*/
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struct epic_rxdesc {
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#if BYTE_ORDER == BIG_ENDIAN
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u_int16_t er_rxlength; /* receive frame length */
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u_int16_t er_rxstatus; /* receive status; see below */
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#else
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u_int16_t er_rxstatus; /* receive status; see below */
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u_int16_t er_rxlength; /* receive frame length */
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#endif
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u_int32_t er_bufaddr; /* buffer address */
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#if BYTE_ORDER == BIG_ENDIAN
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u_int16_t er_control; /* control word; see below */
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u_int16_t er_buflength; /* buffer length */
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#else
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u_int16_t er_buflength; /* buffer length */
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u_int16_t er_control; /* control word; see below */
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#endif
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u_int32_t er_nextdesc; /* next descriptor pointer */
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};
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/* er_rxstatus */
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#define ER_RXSTAT_OWNER 0x8000 /* NIC owns descriptor */
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#define ER_RXSTAT_HDRCOPIED 0x4000 /* rx status posted after hdr copy */
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#define ER_RXSTAT_FRAGLISTERR 0x2000 /* ran out of frags to copy frame */
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#define ER_RXSTAT_NETSTATVALID 0x1000 /* length and status are valid */
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#define ER_RXSTAT_RCVRDIS 0x0040 /* receiver disabled */
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#define ER_RXSTAT_BCAST 0x0020 /* broadcast address recognized */
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#define ER_RXSTAT_MCAST 0x0010 /* multicast address recognized */
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#define ER_RXSTAT_MISSEDPKT 0x0008 /* missed packet */
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#define ER_RXSTAT_CRCERROR 0x0004 /* EPIC or MII asserted CRC error */
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#define ER_RXSTAT_ALIGNERROR 0x0002 /* frame not byte-aligned */
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#define ER_RXSTAT_PKTINTACT 0x0001 /* packet received without error */
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/* er_control */
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#define ER_RXCTL_HEADER 0x0004 /* descriptor is for hdr copy */
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#define ER_RXCTL_LFFORM 0x0002 /* alternate fraglist format */
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#define ER_RXCTL_FRAGLIST 0x0001 /* descriptor points to fraglist */
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#define EPIC_NFRAGS 63 /* maximum number of frags in list */
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/*
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* EPIC fraglist descriptor.
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*/
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struct epic_fraglist {
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u_int32_t ef_nfrags; /* number of frags in list */
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struct {
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u_int32_t ef_addr; /* address of frag */
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u_int32_t ef_length; /* length of frag */
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} ef_frags[EPIC_NFRAGS];
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};
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/*
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* EPIC control registers.
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*/
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#define EPIC_COMMAND 0x00 /* COMMAND */
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#define COMMAND_TXUGO 0x00000080 /* start tx after underrun */
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#define COMMAND_STOP_RDMA 0x00000040 /* stop rx dma */
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#define COMMAND_STOP_TDMA 0x00000020 /* stop tx dma */
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#define COMMAND_NEXTFRAME 0x00000010 /* move onto next rx frame */
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#define COMMAND_RXQUEUED 0x00000008 /* queue a rx descriptor */
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#define COMMAND_TXQUEUED 0x00000004 /* queue a tx descriptor */
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#define COMMAND_START_RX 0x00000002 /* start receiver */
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#define COMMAND_STOP_RX 0x00000001 /* stop receiver */
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#define EPIC_INTSTAT 0x04 /* INTERRUPT STATUS */
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#define INTSTAT_PTA 0x08000000 /* PCI target abort */
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#define INTSTAT_PMA 0x04000000 /* PCI master abort */
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#define INTSTAT_APE 0x02000000 /* PCI address parity error */
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#define INTSTAT_DPE 0x01000000 /* PCI data parity error */
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#define INTSTAT_RSV 0x00800000 /* rx status valid */
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#define INTSTAT_RCTS 0x00400000 /* rx copy threshold status */
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#define INTSTAT_RBE 0x00200000 /* rx buffers empty */
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#define INTSTAT_TCIP 0x00100000 /* tx copy in progress */
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#define INTSTAT_RCIP 0x00080000 /* rx copy in progress */
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#define INTSTAT_TXIDLE 0x00040000 /* transmit idle */
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#define INTSTAT_RXIDLE 0x00020000 /* receive idle */
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#define INTSTAT_INT_ACTV 0x00010000 /* interrupt active */
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#define INTSTAT_GP2_INT 0x00008000 /* gpio2 low (PHY event) */
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#define INTSTAT_FATAL_INT 0x00001000 /* fatal error occured */
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#define INTSTAT_RCT 0x00000800 /* rx copy threshold crossed */
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#define INTSTAT_PREI 0x00000400 /* preemptive interrupt */
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#define INTSTAT_CNT 0x00000200 /* counter overflow */
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#define INTSTAT_TXU 0x00000100 /* transmit underrun */
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#define INTSTAT_TQE 0x00000080 /* transmit queue empty */
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#define INTSTAT_TCC 0x00000040 /* transmit chain complete */
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#define INTSTAT_TXC 0x00000020 /* transmit complete */
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#define INTSTAT_RXE 0x00000010 /* receive error */
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#define INTSTAT_OVW 0x00000008 /* rx buffer overflow */
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#define INTSTAT_RQE 0x00000004 /* receive queue empty */
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#define INTSTAT_HCC 0x00000002 /* header copy complete */
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#define INTSTAT_RCC 0x00000001 /* receive copy complete */
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#define EPIC_INTMASK 0x08 /* INTERRUPT MASK */
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/* Bits 0-15 enable the corresponding interrupt in INTSTAT. */
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#define EPIC_GENCTL 0x0c /* GENERAL CONTROL */
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#define GENCTL_RESET_PHY 0x00004000 /* reset PHY */
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#define GENCTL_SOFT1 0x00002000 /* software use */
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#define GENCTL_SOFT0 0x00001000 /* software use */
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#define GENCTL_MEM_READ_CTL1 0x00000800 /* PCI memory control */
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#define GENCTL_MEM_READ_CTL0 0x00000400 /* (see below) */
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#define GENCTL_RX_FIFO_THRESH1 0x00000200 /* rx fifo thresh */
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#define GENCTL_RX_FIFO_THRESH0 0x00000100 /* (see below) */
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#define GENCTL_BIG_ENDIAN 0x00000020 /* big endian mode */
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#define GENCTL_ONECOPY 0x00000010 /* auto-NEXTFRAME */
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#define GENCTL_POWERDOWN 0x00000008 /* powersave sleep mode */
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#define GENCTL_SOFTINT 0x00000004 /* software-generated intr */
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#define GENCTL_INTENA 0x00000002 /* interrupt enable */
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#define GENCTL_SOFTRESET 0x00000001 /* initialize EPIC */
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/*
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* Explanation of MEMORY READ CONTROL:
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*
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* These bits control which PCI command the transmit DMA will use when
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* bursting data over the PCI bus. When CTL1 is set, the transmit DMA
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* will use the PCI "memory read line" command. When CTL0 is set, the
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* transmit DMA will use the PCI "memory read multiple" command. When
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* neither bit is set, the transmit DMA will use the "memory read" command.
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* Use of "memory read line" or "memory read multiple" may enhance
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* performance on some systems.
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*/
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/*
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* Explanation of RECEIVE FIFO THRESHOLD:
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*
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* Controls the level at which the PCI burst state machine begins to
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* empty the receive FIFO. Default is "1/2 full" (0,1).
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*
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* 0,0 1/4 full 32 bytes
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* 0,1 1/2 full 64 bytes
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* 1,0 3/4 full 96 bytes
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* 1,1 full 128 bytes
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*/
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#define EPIC_NVCTL 0x10 /* NON-VOLATILE CONTROL */
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#define NVCTL_IPG_DLY_MASK 0x00000780 /* interpacket delay gap */
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#define NVCTL_CB_MODE 0x00000040 /* CardBus mode */
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#define NVCTL_GPIO2 0x00000020 /* general purpose i/o */
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#define NVCTL_GPIO1 0x00000010 /* ... */
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#define NVCTL_GPOE2 0x00000008 /* general purpose output ena */
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#define NVCTL_GPOE1 0x00000004 /* ... */
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#define NVCTL_CLKRUNSUPP 0x00000002 /* clock run supported */
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#define NVCTL_ENAMEMMAP 0x00000001 /* enable memory map */
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#define NVCTL_IPG_DLY(x) (((x) & NVCTL_IPG_DLY_MASK) >> 7)
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#define EPIC_EECTL 0x14 /* EEPROM CONTROL */
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#define EECTL_EEPROMSIZE 0x00000040 /* eeprom size; see below */
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#define EECTL_EERDY 0x00000020 /* eeprom ready */
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#define EECTL_EEDO 0x00000010 /* eeprom data out (from) */
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#define EECTL_EEDI 0x00000008 /* eeprom data in (to) */
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#define EECTL_EESK 0x00000004 /* eeprom clock */
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#define EECTL_EECS 0x00000002 /* eeprom chip select */
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#define EECTL_ENABLE 0x00000001 /* eeprom enable */
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/*
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* Explanation of EEPROM SIZE:
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*
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* Indicates the size of the serial EEPROM:
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*
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* 1 16x16 or 64x16
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* 0 128x16 or 256x16
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*/
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/*
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* Serial EEPROM opcodes, including start bit:
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*/
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#define EPIC_EEPROM_OPC_WRITE 0x05
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#define EPIC_EEPROM_OPC_READ 0x06
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#define EPIC_PBLCNT 0x18 /* PBLCNT */
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#define PBLCNT_MASK 0x0000003f /* programmable burst length */
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#define EPIC_TEST 0x1c /* TEST */
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#define TEST_CLOCKTEST 0x00000008
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#define EPIC_CRCCNT 0x20 /* CRC ERROR COUNTER */
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#define CRCCNT_MASK 0x0000000f /* crc errs since last read */
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#define EPIC_ALICNT 0x24 /* FRAME ALIGNMENT ERROR COUNTER */
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#define ALICNT_MASK 0x0000000f /* align errs since last read */
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#define EPIC_MPCNT 0x28 /* MISSED PACKET COUNTER */
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#define MPCNT_MASK 0x0000000f /* miss. pkts since last read */
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#define EPIC_RXFIFO 0x2c
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#define EPIC_MMCTL 0x30 /* MII MANAGEMENT INTERFACE CONTROL */
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#define MMCTL_PHY_ADDR_MASK 0x00003e00 /* phy address field */
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#define MMCTL_PHY_REG_ADDR_MASK 0x000001f0 /* phy register address field */
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#define MMCTL_RESPONDER 0x00000008 /* phy responder */
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#define MMCTL_WRITE 0x00000002 /* write to phy */
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#define MMCTL_READ 0x00000001 /* read from phy */
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#define EPIC_MMDATA 0x34 /* MII MANAGEMENT INTERFACE DATA */
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#define MMDATA_MASK 0x0000ffff /* MII frame data */
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#define EPIC_MIICFG 0x38 /* MII CONFIGURATION */
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#define MIICFG_ALTDIR 0x00000080 /* alternate direction */
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#define MIICFG_ALTDATA 0x00000040 /* alternate data */
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#define MIICFG_ALTCLOCK 0x00000020 /* alternate clock source */
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#define MIICFG_ENASER 0x00000010 /* enable serial manag intf */
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#define MIICFG_PHYPRESENT 0x00000008 /* phy present on MII */
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#define MIICFG_LINKSTATUS 0x00000004 /* 694 link status */
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#define MIICFG_ENABLE 0x00000002 /* enable 694 */
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#define MIICFG_SERMODEENA 0x00000001 /* serial mode enable */
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#define EPIC_IPG 0x3c /* INTERPACKET GAP */
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#define IPG_INTERFRAME_MASK 0x00007f00 /* interframe gap time */
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#define IPG_INTERPKT_MASK 0x000000ff /* interpacket gap time */
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#define EPIC_LAN0 0x40 /* LAN ADDRESS */
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#define EPIC_LAN1 0x44
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#define EPIC_LAN2 0x48
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#define LANn_MASK 0x0000ffff
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/*
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* Explanation of LAN ADDRESS registers:
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*
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* LAN address is described as:
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*
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* 0000 [n1][n0][n3][n2] | 0000 [n5][n4][n7][n6] | 0000 [n9][n8][n11][n10]
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*
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* n == one nibble, mapped as follows:
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*
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* LAN0 [15-12] n3
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* LAN0 [11-8] n2
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* LAN0 [7-4] n1
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* LAN0 [3-0] n0
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* LAN1 [15-12] n7
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* LAN1 [11-8] n6
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* LAN1 [7-4] n5
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* LAN1 [3-0] n4
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* LAN2 [15-12] n11
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* LAN2 [11-8] n10
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* LAN2 [7-4] n9
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* LAN2 [3-0] n8
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*
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* The LAN address is automatically recalled from the EEPROM after a
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* hard reseet.
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*/
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#define EPIC_IDCHK 0x4c /* BOARD ID/CHECKSUM */
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#define IDCHK_ID_MASK 0x0000ff00 /* board ID */
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#define IDCHK_CKSUM_MASK 0x000000ff /* checksum (should be 0xff) */
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#define EPIC_MC0 0x50 /* MULTICAST ADDDRESS HASH TABLE */
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#define EPIC_MC1 0x54
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#define EPIC_MC2 0x58
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#define EPIC_MC3 0x5c
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/*
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* Explanation of MULTICAST ADDRESS HASH TABLE registers:
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*
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* Bits in the hash table are encoded as follows:
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*
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* MC0 [15-0]
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* MC1 [31-16]
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* MC2 [47-32]
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* MC3 [53-48]
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*/
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#define EPIC_RXCON 0x60 /* RECEIVE CONTROL */
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#define RXCON_EXTBUFSIZESEL1 0x00000200 /* ext buf size; see below */
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#define RXCON_EXTBUFSIZESEL0 0x00000100 /* ... */
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#define RXCON_EARLYRXENABLE 0x00000080 /* early receive enable */
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#define RXCON_MONITORMODE 0x00000040 /* monitor mode */
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#define RXCON_PROMISCMODE 0x00000020 /* promiscuous mode */
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#define RXCON_RXINVADDR 0x00000010 /* rx inv individual addr */
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#define RXCON_RXMULTICAST 0x00000008 /* receive multicast */
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#define RXCON_RXBROADCAST 0x00000004 /* receive broadcast */
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#define RXCON_RXRUNT 0x00000002 /* receive runt frames */
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#define RXCON_SAVEERRPKTS 0x00000001 /* save errored packets */
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/*
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* Explanation of EXTERNAL BUFFER SIZE SELECT:
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*
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* 0,0 external buffer access is disabled
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* 0,1 16k
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* 1,0 32k
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* 1,1 128k
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*/
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#define EPIC_RXSTAT 0x64 /* RECEIVE STATUS */
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#define EPIC_RXCNT 0x68
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#define EPIC_RXTEST 0x6c
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#define EPIC_TXCON 0x70 /* TRANSMIT CONTROL */
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#define TXCON_SLOTTIME_MASK 0x000000f8 /* slot time */
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#define TXCON_LOOPBACK_D2 0x00000004 /* loopback mode bit 2 */
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#define TXCON_LOOPBACK_D1 0x00000002 /* loopback mode bit 1 */
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#define TXCON_EARLYTX_ENABLE 0x00000001 /* early transmit enable */
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/*
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* Explanation of LOOPBACK MODE BIT:
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*
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* 0,0 normal operation
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* 0,1 internal loopback (before PHY)
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* 1,0 external loopback (after PHY)
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* 1,1 full duplex - decouples transmit and receive blocks
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*/
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#define EPIC_TXSTAT 0x74 /* TRANSMIT STATUS */
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#define EPIC_TDPAR 0x78
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#define EPIC_TXTEST 0x7c
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#define EPIC_PRFDAR 0x80
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#define EPIC_PRCDAR 0x84 /* PCI RECEIVE CURRENT DESCRIPTOR ADDR */
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#define EPIC_PRHDAR 0x88
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#define EPIC_PRFLAR 0x8c
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#define EPIC_PRDLGTH 0x90
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#define EPIC_PRFCNT 0x94
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#define EPIC_PRLCAR 0x98
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#define EPIC_PRLPAR 0x9c
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#define EPIC_PREFAR 0xa0
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#define EPIC_PRSTAT 0xa4 /* PCI RECEIVE DMA STATUS */
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#define EPIC_PRBUF 0xa8
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#define EPIC_RDNCAR 0xac
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#define EPIC_PRCPTHR 0xb0 /* PCI RECEIVE COPY THRESHOLD */
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#define EPIC_ROMDATA 0xb4
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#define EPIC_PREEMPR 0xbc
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#define EPIC_PTFDAR 0xc0
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#define EPIC_PTCDAR 0xc4 /* PCI TRANSMIT CURRENT DESCRIPTOR ADDR */
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#define EPIC_PTHDAR 0xc8
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#define EPIC_PTFLAR 0xcc
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#define EPIC_PTDLGTH 0xd0
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#define EPIC_PTFCNT 0xd4
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#define EPIC_PTLCAR 0xd8
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#define EPIC_ETXTHR 0xdc /* EARLY TRANSMIT THRESHOLD */
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#define EPIC_PTETXC 0xe0
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#define EPIC_PTSTAT 0xe4
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#define EPIC_PTBUF 0xe8
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#define EPIC_PTFDAR2 0xec
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#define EPIC_FEVTR 0xf0 /* FEVTR (CardBus) */
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#define EPIC_FEVTRMSKR 0xf4 /* FEVTRMSKR (CardBus) */
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#define EPIC_FPRSTSTR 0xf8 /* FPRSTR (CardBus) */
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#define EPIC_FFRCEVTR 0xfc /* PPRCEVTR (CardBus) */
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/*
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* EEPROM format:
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*
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* Word Bits Description
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* ---- ---- -----------
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* 0 7-0 LAN Address Byte 0
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* 0 15-8 LAN Address Byte 1
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* 1 7-0 LAN Address Byte 2
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* 1 15-8 LAN Address Byte 3
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* 2 7-0 LAN Address Byte 4
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* 2 15-8 LAN Address Byte 5
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* 3 7-0 Board ID
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* 3 15-8 Checksum
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* 4 5-0 Non-Volatile Control Register Contents
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* 5 7-0 PCI Minimum Grant Desired Setting
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* 5 15-8 PCI Maximum Latency Desired Setting
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* 6 15-0 Subsystem Vendor ID
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* 7 14-0 Subsystem ID
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*/
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#endif /* _DEV_IC_SMC83C170REG_H_ */
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