647 lines
16 KiB
C
647 lines
16 KiB
C
/* $NetBSD: machdep.c,v 1.11 2003/04/26 11:05:11 ragge Exp $ */
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/*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_marvell.h"
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#include "opt_ev64260.h"
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#include "opt_compat_netbsd.h"
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#include "opt_ddb.h"
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#include "opt_inet.h"
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#include "opt_ccitt.h"
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#include "opt_iso.h"
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#include "opt_ns.h"
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#include "opt_ipkdb.h"
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/mount.h>
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#include <sys/msgbuf.h>
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#include <sys/proc.h>
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#include <sys/reboot.h>
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#include <sys/extent.h>
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#include <sys/syslog.h>
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#include <sys/systm.h>
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#include <sys/termios.h>
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#include <sys/ksyms.h>
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#include <uvm/uvm.h>
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#include <uvm/uvm_extern.h>
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#include <net/netisr.h>
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#include <machine/bus.h>
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#include <machine/db_machdep.h>
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#include <machine/intr.h>
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#include <machine/pmap.h>
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#include <machine/powerpc.h>
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#include <machine/trap.h>
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#include <powerpc/oea/bat.h>
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#include <powerpc/marvell/watchdog.h>
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#include <ddb/db_extern.h>
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#include <dev/cons.h>
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#include "vga.h"
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#if (NVGA > 0)
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#include <dev/ic/mc6845reg.h>
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#include <dev/ic/pcdisplayvar.h>
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#include <dev/ic/vgareg.h>
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#include <dev/ic/vgavar.h>
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#endif
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#include "isa.h"
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#if (NISA > 0)
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void isa_intr_init(void);
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#endif
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#include "pckbc.h"
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#if (NPCKBC > 0)
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#include <dev/isa/isareg.h>
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#include <dev/ic/i8042reg.h>
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#include <dev/ic/pckbcvar.h>
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#endif
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#include "com.h"
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#if (NCOM > 0)
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#include <dev/ic/comreg.h>
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#include <dev/ic/comvar.h>
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#endif
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#include <dev/marvell/gtreg.h>
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#include <dev/marvell/gtvar.h>
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#include <dev/marvell/gtethreg.h>
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#include "gtmpsc.h"
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#if (NGTMPSC > 0)
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#include <dev/marvell/gtsdmareg.h>
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#include <dev/marvell/gtmpscreg.h>
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#include <dev/marvell/gtmpscvar.h>
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#endif
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#include "ksyms.h"
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/*
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* Global variables used here and there
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*/
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extern struct user *proc0paddr;
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#define PMONMEMREGIONS 32
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struct mem_region physmemr[PMONMEMREGIONS], availmemr[PMONMEMREGIONS];
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char *bootpath;
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void initppc(u_int, u_int, u_int, void *); /* Called from locore */
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void strayintr(int);
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int lcsplx(int);
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void gt_bus_space_init(void);
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void gt_find_memory(bus_space_tag_t, bus_space_handle_t, paddr_t);
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void gt_halt(bus_space_tag_t, bus_space_handle_t);
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void return_to_dink(int);
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void calc_delayconst(void);
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void kcomcnputs(dev_t, const char *);
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struct powerpc_bus_space gt_pci0_mem_bs_tag = {
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_BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_pci0_io_bs_tag = {
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_BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_pci1_mem_bs_tag = {
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_BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_pci1_io_bs_tag = {
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_BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_obio0_bs_tag = {
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_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO0_STRIDE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_obio1_bs_tag = {
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_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO1_STRIDE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_obio2_bs_tag = {
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_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO2_STRIDE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_obio3_bs_tag = {
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_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE|OBIO3_STRIDE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_bootcs_bs_tag = {
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_BUS_SPACE_BIG_ENDIAN|_BUS_SPACE_MEM_TYPE,
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0x00000000, 0x00000000, 0x00000000,
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};
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struct powerpc_bus_space gt_mem_bs_tag = {
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_BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE,
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GT_BASE, 0x00000000, 0x00010000,
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};
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bus_space_handle_t gt_memh;
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struct powerpc_bus_space *obio_bs_tags[5] = {
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>_obio0_bs_tag, >_obio1_bs_tag, >_obio2_bs_tag,
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>_obio3_bs_tag, >_bootcs_bs_tag
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};
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static char ex_storage[10][EXTENT_FIXED_STORAGE_SIZE(8)]
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__attribute__((aligned(8)));
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const struct gt_decode_info {
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bus_addr_t low_decode;
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bus_addr_t high_decode;
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} decode_regs[] = {
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{ GT_SCS0_Low_Decode, GT_SCS0_High_Decode },
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{ GT_SCS1_Low_Decode, GT_SCS1_High_Decode },
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{ GT_SCS2_Low_Decode, GT_SCS2_High_Decode },
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{ GT_SCS3_Low_Decode, GT_SCS3_High_Decode },
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{ GT_CS0_Low_Decode, GT_CS0_High_Decode },
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{ GT_CS1_Low_Decode, GT_CS1_High_Decode },
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{ GT_CS2_Low_Decode, GT_CS2_High_Decode },
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{ GT_CS3_Low_Decode, GT_CS3_High_Decode },
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{ GT_BootCS_Low_Decode, GT_BootCS_High_Decode },
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};
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void
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initppc(startkernel, endkernel, args, btinfo)
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u_int startkernel, endkernel, args;
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void *btinfo;
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{
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oea_batinit(0xf0000000, BAT_BL_256M);
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oea_init((void (*)(void))ext_intr);
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calc_delayconst(); /* Set CPU clock */
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DELAY(100000);
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gt_bus_space_init();
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gt_find_memory(>_mem_bs_tag, gt_memh, roundup(endkernel, PAGE_SIZE));
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gt_halt(>_mem_bs_tag, gt_memh);
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/*
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* Now that we known how much memory, reinit the bats.
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*/
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oea_batinit(0xf0000000, BAT_BL_256M);
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consinit();
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#if (NISA > 0)
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isa_intr_init();
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#endif
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/*
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* Set the page size.
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*/
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uvm_setpagesize();
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/*
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* Initialize pmap module.
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*/
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pmap_bootstrap(startkernel, endkernel);
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#if NKSYMS || defined(DDB) || defined(LKM)
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{
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extern void *startsym, *endsym;
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ksyms_init((int)((u_int)endsym - (u_int)startsym),
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startsym, endsym);
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}
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#endif
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#ifdef IPKDB
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/*
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* Now trap to IPKDB
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*/
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ipkdb_init();
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if (boothowto & RB_KDB)
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ipkdb_connect(0);
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#endif
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}
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void
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mem_regions(struct mem_region **mem, struct mem_region **avail)
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{
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*mem = physmemr;
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*avail = availmemr;
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}
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static __inline void
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gt_record_memory(int j, paddr_t start, paddr_t end, paddr_t endkernel)
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{
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physmemr[j].start = start;
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physmemr[j].size = end - start;
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if (start < endkernel)
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start = endkernel;
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availmemr[j].start = start;
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availmemr[j].size = end - start;
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}
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void
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gt_find_memory(bus_space_tag_t memt, bus_space_handle_t memh,
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paddr_t endkernel)
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{
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paddr_t start, end;
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int i, j = 0, first = 1;
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/*
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* Round kernel end to a page boundary.
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*/
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for (i = 0; i < 4; i++) {
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paddr_t nstart, nend;
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nstart = GT_LowAddr_GET(bus_space_read_4(>_mem_bs_tag,
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gt_memh, decode_regs[i].low_decode));
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nend = GT_HighAddr_GET(bus_space_read_4(>_mem_bs_tag,
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gt_memh, decode_regs[i].high_decode)) + 1;
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if (nstart >= nend)
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continue;
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if (first) {
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/*
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* First entry? Just remember it.
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*/
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start = nstart;
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end = nend;
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first = 0;
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} else if (nstart == end) {
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/*
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* Contiguous? Just update the end.
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*/
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end = nend;
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} else {
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/*
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* Disjoint? record it.
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*/
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gt_record_memory(j, start, end, endkernel);
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start = nstart;
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end = nend;
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j++;
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}
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}
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gt_record_memory(j, start, end, endkernel);
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}
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/*
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* Machine dependent startup code.
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*/
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void
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cpu_startup(void)
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{
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register_t msr;
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oea_startup(NULL);
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/*
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* Now that we have VM, malloc()s are OK in bus_space.
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*/
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bus_space_mallocok();
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/*
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* Now allow hardware interrupts.
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*/
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splhigh();
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__asm __volatile ("mfmsr %0; ori %0,%0,%1; mtmsr %0"
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: "=r"(msr)
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: "K"(PSL_EE));
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}
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/*
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* consinit
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* Initialize system console.
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*/
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void
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consinit(void)
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{
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#ifdef MPSC_CONSOLE
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/* PMON using MPSC0 @ 9600 */
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gtmpsccnattach(>_mem_bs_tag, gt_memh, MPSC_CONSOLE, 9600,
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(TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8);
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#else
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/* PPCBOOT using COM1 @ 57600 */
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comcnattach(>_obio2_bs_tag, 0, 57600, COM_FREQ*2,
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(TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8);
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#endif
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}
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#if (NPCKBC > 0) && (NPCKBD == 0)
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/*
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* glue code to support old console code with the
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* mi keyboard controller driver
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*/
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int
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pckbc_machdep_cnattach(pckbc_tag_t kbctag, pckbc_slot_t kbcslot)
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{
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#if (NPC > 0)
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return (pcconskbd_cnattach(kbctag, kbcslot));
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#else
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return (ENXIO);
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#endif
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}
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#endif
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/*
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* Stray interrupts.
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*/
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void
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strayintr(int irq)
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{
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log(LOG_ERR, "stray interrupt %d\n", irq);
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}
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/*
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* Halt or reboot the machine after syncing/dumping according to howto.
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*/
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void
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cpu_reboot(int howto, char *what)
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{
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static int syncing;
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static char str[256];
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char *ap = str, *ap1 = ap;
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boothowto = howto;
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if (!cold && !(howto & RB_NOSYNC) && !syncing) {
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syncing = 1;
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vfs_shutdown(); /* sync */
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resettodr(); /* set wall clock */
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}
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splhigh();
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if (howto & RB_HALT) {
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doshutdownhooks();
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printf("halted\n\n");
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cnhalt();
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while(1);
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}
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if (!cold && (howto & RB_DUMP))
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oea_dumpsys();
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doshutdownhooks();
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printf("rebooting\n\n");
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if (what && *what) {
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if (strlen(what) > sizeof str - 5)
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printf("boot string too large, ignored\n");
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else {
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strcpy(str, what);
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ap1 = ap = str + strlen(str);
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*ap++ = ' ';
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}
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}
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*ap++ = '-';
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if (howto & RB_SINGLE)
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*ap++ = 's';
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if (howto & RB_KDB)
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*ap++ = 'd';
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*ap++ = 0;
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if (ap[-2] == '-')
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*ap1 = 0;
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#if 0
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{
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void mvpppc_reboot(void);
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mvpppc_reboot();
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}
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#endif
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gt_watchdog_reset();
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/* NOTREACHED */
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while (1);
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}
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int
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lcsplx(int ipl)
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{
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return spllower(ipl);
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}
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void
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gt_halt(bus_space_tag_t gt_memt, bus_space_handle_t gt_memh)
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{
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int i;
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u_int32_t data;
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/*
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* Shut down the MPSC ports
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*/
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for (i = 0; i < 2; i++) {
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bus_space_write_4(gt_memt, gt_memh,
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SDMA_U_SDCM(i), SDMA_SDCM_AR|SDMA_SDCM_AT);
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for (;;) {
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data = bus_space_read_4(gt_memt, gt_memh,
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SDMA_U_SDCM(i));
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if (((SDMA_SDCM_AR|SDMA_SDCM_AT) & data) == 0)
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break;
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}
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}
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/*
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* Shut down the Ethernets
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*/
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for (i = 0; i < 3; i++) {
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bus_space_write_4(gt_memt, gt_memh,
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ETH_ESDCMR(2), ETH_ESDCMR_AR|ETH_ESDCMR_AT);
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for (;;) {
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data = bus_space_read_4(gt_memt, gt_memh,
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ETH_ESDCMR(i));
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if (((ETH_ESDCMR_AR|ETH_ESDCMR_AT) & data) == 0)
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break;
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}
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data = bus_space_read_4(gt_memt, gt_memh, ETH_EPCR(i));
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data &= ~ETH_EPCR_EN;
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bus_space_write_4(gt_memt, gt_memh, ETH_EPCR(i), data);
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}
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}
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int
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gtget_macaddr(struct gt_softc *gt, int macno, char *enaddr)
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{
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enaddr[0] = 0x02;
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enaddr[1] = 0x00;
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enaddr[2] = 0x04;
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enaddr[3] = 0x00;
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enaddr[4] = 0x00;
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enaddr[5] = 0x04 + macno;
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return 0;
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}
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void
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gt_bus_space_init(void)
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{
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bus_space_tag_t gt_memt = >_mem_bs_tag;
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const struct gt_decode_info *di;
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uint32_t datal, datah;
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int error;
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int bs = 0;
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int j;
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|
error = bus_space_init(>_mem_bs_tag, "gtmem",
|
|
ex_storage[bs], sizeof(ex_storage[bs]));
|
|
|
|
error = bus_space_map(gt_memt, 0, 0x10000, 0, >_memh);
|
|
|
|
for (j = 0, di = &decode_regs[4]; j < 5; j++, di++) {
|
|
struct powerpc_bus_space *memt = obio_bs_tags[j];
|
|
datal = bus_space_read_4(gt_memt, gt_memh, di->low_decode);
|
|
datah = bus_space_read_4(gt_memt, gt_memh, di->high_decode);
|
|
|
|
if (GT_LowAddr_GET(datal) >= GT_HighAddr_GET(datal)) {
|
|
obio_bs_tags[j] = NULL;
|
|
continue;
|
|
}
|
|
memt->pbs_offset = GT_LowAddr_GET(datal);
|
|
memt->pbs_limit = GT_HighAddr_GET(datah) + 1 -
|
|
memt->pbs_offset;
|
|
|
|
error = bus_space_init(memt, "obio2",
|
|
ex_storage[bs], sizeof(ex_storage[bs]));
|
|
bs++;
|
|
}
|
|
|
|
datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode);
|
|
datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode);
|
|
#if defined(GT_PCI0_MEMBASE)
|
|
datal &= ~0xfff;
|
|
datal |= (GT_PCI0_MEMBASE >> 20);
|
|
bus_space_write_4(gt_memt, gt_memh, GT_PCI0_Mem0_Low_Decode, datal);
|
|
#endif
|
|
#if defined(GT_PCI0_MEMSIZE)
|
|
datah &= ~0xfff;
|
|
datah |= (GT_PCI0_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20;
|
|
bus_space_write_4(gt_memt, gt_memh, GT_PCI0_Mem0_High_Decode, datal);
|
|
#endif
|
|
gt_pci0_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal);
|
|
gt_pci0_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1;
|
|
|
|
error = bus_space_init(>_pci0_mem_bs_tag, "pci0-mem",
|
|
ex_storage[bs], sizeof(ex_storage[bs]));
|
|
bs++;
|
|
|
|
/*
|
|
* Make sure PCI0 Memory is BAT mapped.
|
|
*/
|
|
if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal))
|
|
oea_iobat_add(gt_pci0_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M);
|
|
|
|
/*
|
|
* Make sure that I/O space start at 0.
|
|
*/
|
|
bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0);
|
|
|
|
datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode);
|
|
datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode);
|
|
#if defined(GT_PCI0_IOBASE)
|
|
datal &= ~0xfff;
|
|
datal |= (GT_PCI0_IOBASE >> 20);
|
|
bus_space_write_4(gt_memt, gt_memh, GT_PCI0_IO_Low_Decode, datal);
|
|
#endif
|
|
#if defined(GT_PCI0_IOSIZE)
|
|
datah &= ~0xfff;
|
|
datah |= (GT_PCI0_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20;
|
|
bus_space_write_4(gt_memt, gt_memh, GT_PCI0_IO_High_Decode, datal);
|
|
#endif
|
|
gt_pci0_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal);
|
|
gt_pci0_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 -
|
|
gt_pci0_io_bs_tag.pbs_offset;
|
|
|
|
error = bus_space_init(>_pci0_io_bs_tag, "pci0-ioport",
|
|
ex_storage[bs], sizeof(ex_storage[bs]));
|
|
bs++;
|
|
|
|
#if 0
|
|
error = extent_alloc_region(gt_pci0_io_bs_tag.pbs_extent,
|
|
0x10000, 0x7F0000, EX_NOWAIT);
|
|
if (error)
|
|
panic("gt_bus_space_init: can't block out reserved "
|
|
"I/O space 0x10000-0x7fffff: error=%d\n", error);
|
|
#endif
|
|
|
|
datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode);
|
|
datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode);
|
|
#if defined(GT_PCI1_MEMBASE)
|
|
datal &= ~0xfff;
|
|
datal |= (GT_PCI1_MEMBASE >> 20);
|
|
bus_space_write_4(gt_memt, gt_memh, GT_PCI1_Mem0_Low_Decode, datal);
|
|
#endif
|
|
#if defined(GT_PCI1_MEMSIZE)
|
|
datah &= ~0xfff;
|
|
datah |= (GT_PCI1_MEMSIZE + GT_LowAddr_GET(datal) - 1) >> 20;
|
|
bus_space_write_4(gt_memt, gt_memh, GT_PCI1_Mem0_High_Decode, datal);
|
|
#endif
|
|
gt_pci1_mem_bs_tag.pbs_base = GT_LowAddr_GET(datal);
|
|
gt_pci1_mem_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1;
|
|
|
|
error = bus_space_init(>_pci1_mem_bs_tag, "pci1-mem",
|
|
ex_storage[bs], sizeof(ex_storage[bs]));
|
|
bs++;
|
|
|
|
/*
|
|
* Make sure PCI1 Memory is BAT mapped.
|
|
*/
|
|
if (GT_LowAddr_GET(datal) < GT_HighAddr_GET(datal))
|
|
oea_iobat_add(gt_pci1_mem_bs_tag.pbs_base & SEGMENT_MASK, BAT_BL_256M);
|
|
|
|
/*
|
|
* Make sure that I/O space start at 0.
|
|
*/
|
|
bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Remap, 0);
|
|
|
|
datal = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode);
|
|
datah = bus_space_read_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode);
|
|
#if defined(GT_PCI1_IOBASE)
|
|
datal &= ~0xfff;
|
|
datal |= (GT_PCI1_IOBASE >> 20);
|
|
bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_Low_Decode, datal);
|
|
#endif
|
|
#if defined(GT_PCI1_IOSIZE)
|
|
datah &= ~0xfff;
|
|
datah |= (GT_PCI1_IOSIZE + GT_LowAddr_GET(datal) - 1) >> 20;
|
|
bus_space_write_4(gt_memt, gt_memh, GT_PCI1_IO_High_Decode, datal);
|
|
#endif
|
|
gt_pci1_io_bs_tag.pbs_offset = GT_LowAddr_GET(datal);
|
|
gt_pci1_io_bs_tag.pbs_limit = GT_HighAddr_GET(datah) + 1 -
|
|
gt_pci1_io_bs_tag.pbs_offset;
|
|
|
|
error = bus_space_init(>_pci1_io_bs_tag, "pci1-ioport",
|
|
ex_storage[bs], sizeof(ex_storage[bs]));
|
|
bs++;
|
|
|
|
#if 0
|
|
error = extent_alloc_region(gt_pci1_io_bs_tag.pbs_extent,
|
|
0x10000, 0x7F0000, EX_NOWAIT);
|
|
if (error)
|
|
panic("gt_bus_space_init: can't block out reserved "
|
|
"I/O space 0x10000-0x7fffff: error=%d\n", error);
|
|
#endif
|
|
}
|