148 lines
5.0 KiB
C
148 lines
5.0 KiB
C
/* $NetBSD: sdmmcchip.h,v 1.10 2019/10/23 05:20:52 hkenken Exp $ */
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/* $OpenBSD: sdmmcchip.h,v 1.3 2007/05/31 10:09:01 uwe Exp $ */
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/*
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* Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _SDMMC_CHIP_H_
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#define _SDMMC_CHIP_H_
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#include <sys/device.h>
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#include <sys/bus.h>
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struct sdmmc_command;
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typedef struct sdmmc_chip_functions *sdmmc_chipset_tag_t;
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typedef struct sdmmc_spi_chip_functions *sdmmc_spi_chipset_tag_t;
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typedef void *sdmmc_chipset_handle_t;
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struct sdmmc_chip_functions {
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/* host controller reset */
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int (*host_reset)(sdmmc_chipset_handle_t);
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/* host capabilities */
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uint32_t (*host_ocr)(sdmmc_chipset_handle_t);
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int (*host_maxblklen)(sdmmc_chipset_handle_t);
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/* card detection */
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int (*card_detect)(sdmmc_chipset_handle_t);
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/* write protect */
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int (*write_protect)(sdmmc_chipset_handle_t);
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/* bus power, clock frequency, width and ROD(OpenDrain/PushPull) */
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int (*bus_power)(sdmmc_chipset_handle_t, uint32_t);
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int (*bus_clock)(sdmmc_chipset_handle_t, int);
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int (*bus_width)(sdmmc_chipset_handle_t, int);
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int (*bus_rod)(sdmmc_chipset_handle_t, int);
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/* command execution */
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void (*exec_command)(sdmmc_chipset_handle_t,
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struct sdmmc_command *);
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/* card interrupt */
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void (*card_enable_intr)(sdmmc_chipset_handle_t, int);
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void (*card_intr_ack)(sdmmc_chipset_handle_t);
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/* UHS functions */
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int (*signal_voltage)(sdmmc_chipset_handle_t, int);
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int (*bus_clock_ddr)(sdmmc_chipset_handle_t, int, bool);
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int (*execute_tuning)(sdmmc_chipset_handle_t, int);
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/* hardware reset */
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void (*hw_reset)(sdmmc_chipset_handle_t);
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};
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/* host controller reset */
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#define sdmmc_chip_host_reset(tag, handle) \
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((tag)->host_reset((handle)))
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/* host capabilities */
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#define sdmmc_chip_host_ocr(tag, handle) \
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((tag)->host_ocr((handle)))
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#define sdmmc_chip_host_maxblklen(tag, handle) \
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((tag)->host_maxblklen((handle)))
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/* card detection */
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#define sdmmc_chip_card_detect(tag, handle) \
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((tag)->card_detect((handle)))
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/* write protect */
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#define sdmmc_chip_write_protect(tag, handle) \
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((tag)->write_protect((handle)))
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/* bus power, clock frequency, width and rod */
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#define sdmmc_chip_bus_power(tag, handle, ocr) \
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((tag)->bus_power((handle), (ocr)))
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#define sdmmc_chip_bus_clock(tag, handle, freq, ddr) \
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((tag)->bus_clock_ddr ? (tag)->bus_clock_ddr((handle), (freq), (ddr)) : ((ddr) ? EINVAL : ((tag)->bus_clock((handle), (freq)))))
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#define sdmmc_chip_bus_width(tag, handle, width) \
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((tag)->bus_width((handle), (width)))
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#define sdmmc_chip_bus_rod(tag, handle, width) \
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((tag)->bus_rod((handle), (width)))
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/* command execution */
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#define sdmmc_chip_exec_command(tag, handle, cmdp) \
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((tag)->exec_command((handle), (cmdp)))
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/* card interrupt */
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#define sdmmc_chip_card_enable_intr(tag, handle, enable) \
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((tag)->card_enable_intr((handle), (enable)))
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#define sdmmc_chip_card_intr_ack(tag, handle) \
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((tag)->card_intr_ack((handle)))
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/* UHS functions */
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#define sdmmc_chip_signal_voltage(tag, handle, voltage) \
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((tag)->signal_voltage ? (tag)->signal_voltage((handle), (voltage)) : EINVAL)
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#define sdmmc_chip_execute_tuning(tag, handle, timing) \
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((tag)->execute_tuning ? (tag)->execute_tuning((handle), (timing)) : EINVAL)
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/* hardware reset */
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#define sdmmc_chip_hw_reset(tag, handle) \
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((tag)->hw_reset ? (tag)->hw_reset((handle)) : /*CONSTCOND*/0)
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/* clock frequencies for sdmmc_chip_bus_clock() */
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#define SDMMC_SDCLK_OFF 0
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#define SDMMC_SDCLK_400K 400
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/* voltage levels for sdmmc_chip_signal_voltage() */
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#define SDMMC_SIGNAL_VOLTAGE_330 0
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#define SDMMC_SIGNAL_VOLTAGE_180 1
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/* timings for sdmmc_chip_execute_tuning() */
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#define SDMMC_TIMING_UHS_SDR50 0
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#define SDMMC_TIMING_UHS_SDR104 1
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#define SDMMC_TIMING_MMC_HS200 2
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/* SPI mode */
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struct sdmmc_spi_chip_functions {
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/* card initialize */
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void (*initialize)(sdmmc_chipset_handle_t);
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};
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#define sdmmc_spi_chip_initialize(tag, handle) \
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((tag)->initialize((handle)))
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struct sdmmcbus_attach_args {
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const char *saa_busname;
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sdmmc_chipset_tag_t saa_sct;
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sdmmc_spi_chipset_tag_t saa_spi_sct;
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sdmmc_chipset_handle_t saa_sch;
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bus_dma_tag_t saa_dmat;
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u_int saa_clkmin;
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u_int saa_clkmax;
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uint32_t saa_caps; /* see sdmmc_softc.sc_caps */
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uint32_t saa_max_seg;
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};
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void sdmmc_needs_discover(device_t);
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void sdmmc_card_intr(device_t);
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void sdmmc_delay(u_int);
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#endif /* _SDMMC_CHIP_H_ */
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