0fb6b9a8f8
Rather than an "iointr" routine that decomposes a vector into an IRQ, we maintain a vector table directly, hooking up each "iointr" routine at the correct vector. This also allows us to hook device interrupts up to specific vectors (c.f. Jensen). We can shave even more cycles off, here, and I will, but it requires some changes to the alpha_shared_intr stuff.
100 lines
3.5 KiB
C
100 lines
3.5 KiB
C
/* $NetBSD: dwlpxvar.h,v 1.8 2001/07/27 00:25:20 thorpej Exp $ */
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/*
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* Copyright (c) 1997 by Matthew Jacob
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* NASA AMES Research Center.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <dev/pci/pcivar.h>
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#include <sys/extent.h>
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#include <alpha/pci/pci_sgmap_pte32.h>
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#define _FSTORE (EXTENT_FIXED_STORAGE_SIZE(8) / sizeof(long))
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/*
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* DWLPX configuration.
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*/
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struct dwlpx_config {
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int cc_initted;
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struct alpha_bus_space cc_iot;
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struct alpha_bus_space cc_memt;
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struct extent * cc_io_ex;
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struct extent * cc_d_mem_ex;
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struct extent * cc_s_mem_ex;
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struct alpha_pci_chipset cc_pc;
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struct dwlpx_softc * cc_sc; /* back pointer */
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long cc_io_exstorage[_FSTORE];
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long cc_dmem_exstorage[_FSTORE];
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long cc_smem_exstorage[_FSTORE];
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unsigned long cc_sysbase; /* shorthand */
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struct alpha_bus_dma_tag cc_dmat_direct;
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struct alpha_bus_dma_tag cc_dmat_sgmap;
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struct alpha_sgmap cc_sgmap;
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};
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struct dwlpx_softc {
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struct device dwlpx_dev;
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struct dwlpx_config dwlpx_cc; /* config info */
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u_int16_t dwlpx_dtype; /* Node Type */
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u_int8_t dwlpx_node; /* TurboLaser Node */
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u_int8_t dwlpx_hosenum; /* Hose Number */
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u_int8_t dwlpx_nhpc; /* # of hpcs */
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u_int8_t dwlpx_sgmapsz; /* size of SGMAP */
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};
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#define DWLPX_NONE 0
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#define DWLPX_SG32K 1
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#define DWLPX_SG64K 2
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#define DWLPX_SG128K 3
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void dwlpx_init __P((struct dwlpx_softc *));
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void dwlpx_pci_init __P((pci_chipset_tag_t, void *));
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void dwlpx_dma_init __P((struct dwlpx_config *));
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void dwlpx_bus_io_init __P((bus_space_tag_t, void *));
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void dwlpx_bus_mem_init __P((bus_space_tag_t, void *));
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/*
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* Each DWLPX supports up to 15 devices, 12 of which are PCI slots.
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*
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* Since the STD I/O modules in slots 12-14 are really a PCI-EISA
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* bridge, we'll punt on those for the moment.
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*/
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#define DWLPX_MAXDEV 12
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#define DWLPX_NIONODE 5
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#define DWLPX_NHOSE 4
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/*
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* Default values to put into DWLPX IMASK register(s)
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*/
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#define DWLPX_IMASK_DFLT \
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(1 << 24) | /* IPL 17 for error interrupts */ \
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(1 << 17) | /* IPL 14 for device interrupts */ \
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(1 << 16) /* Enable Error Interrupts */
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