85716c44d5
- Adapt int(4) to handle the INT1 chip
- Move generic rtc clocks out of hpc/ and into dev/
- Handle the very strangely wired eeprom and other bits in arcemu
- Sprinkle MACH_SGI_IP6 as necessary
- Enable IP6/IP10 devices in GENERIC32_IP12. Yes, the naming is poor but
there's no winning with kernel/hw compatibility on sgimips...
Tested on my 4D/25. Doesn't (appear to) break macallan@'s IP22.
58 lines
2.3 KiB
C
58 lines
2.3 KiB
C
/* $NetBSD: int2reg.h,v 1.5 2009/02/12 06:33:57 rumble Exp $ */
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/*
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* Copyright (c) 2004 Christopher SEKIYA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#if !defined(_ARCH_SGIMIPS_DEV_INT2_H_)
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#define _ARCH_SGIMIPS_DEV_INT2_H_
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/* The INT has known locations on all SGI machines */
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#define INT2_IP12 0x1fb801c0
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#define INT2_IP20 0x1fb801c0
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#define INT2_IP22 0x1fbd9000
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#define INT2_IP24 0x1fbd9880
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/* The following registers are all 8 bit. */
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#define INT2_LOCAL0_STATUS 0x03
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#define INT2_LOCAL0_STATUS_FIFO 0x01
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#define INT2_LOCAL0_MASK 0x07
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#define INT2_LOCAL1_STATUS 0x0b
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#define INT2_LOCAL1_MASK 0x0f
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#define INT2_MAP_STATUS 0x13
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#define INT2_MAP_MASK0 0x17
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#define INT2_MAP_MASK1 0x1b
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#define INT2_MAP_POL 0x1f
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#define INT2_TIMER_CLEAR 0x23
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#define INT2_ERROR_STATUS 0x27
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#define INT2_TIMER_0 0x33
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#define INT2_TIMER_1 0x37
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#define INT2_TIMER_2 0x3b
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#define INT2_TIMER_CONTROL 0x3f
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#endif /* _ARCH_SGIMIPS_DEV_INT2_H_ */
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