272 lines
7.8 KiB
C
272 lines
7.8 KiB
C
/* $NetBSD: via82c586.c,v 1.3 2001/01/05 19:08:04 tsutsui Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Support for the VIA 82c586 PCI-ISA bridge interrupt controller.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <machine/intr.h>
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#include <machine/bus.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <i386/pci/pci_intr_fixup.h>
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#include <i386/pci/via82c586reg.h>
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#include <i386/pci/piixvar.h>
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int via82c586_getclink __P((pciintr_icu_handle_t, int, int *));
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int via82c586_get_intr __P((pciintr_icu_handle_t, int, int *));
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int via82c586_set_intr __P((pciintr_icu_handle_t, int, int));
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int via82c586_get_trigger __P((pciintr_icu_handle_t, int, int *));
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int via82c586_set_trigger __P((pciintr_icu_handle_t, int, int));
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const struct pciintr_icu via82c586_pci_icu = {
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via82c586_getclink,
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via82c586_get_intr,
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via82c586_set_intr,
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via82c586_get_trigger,
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via82c586_set_trigger,
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};
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const int vp3_cfg_trigger_shift[] = {
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VP3_CFG_TRIGGER_SHIFT_PIRQA,
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VP3_CFG_TRIGGER_SHIFT_PIRQB,
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VP3_CFG_TRIGGER_SHIFT_PIRQC,
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VP3_CFG_TRIGGER_SHIFT_PIRQD,
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};
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#define VP3_TRIGGER(reg, pirq) (((reg) >> vp3_cfg_trigger_shift[(pirq)]) & \
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VP3_CFG_TRIGGER_MASK)
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const int vp3_cfg_intr_shift[] = {
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VP3_CFG_INTR_SHIFT_PIRQA,
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VP3_CFG_INTR_SHIFT_PIRQB,
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VP3_CFG_INTR_SHIFT_PIRQC,
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VP3_CFG_INTR_SHIFT_PIRQD,
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};
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#define VP3_PIRQ(reg, pirq) (((reg) >> vp3_cfg_intr_shift[(pirq)]) & \
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VP3_CFG_INTR_MASK)
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int
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via82c586_init(pc, iot, tag, ptagp, phandp)
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pci_chipset_tag_t pc;
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bus_space_tag_t iot;
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pcitag_t tag;
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pciintr_icu_tag_t *ptagp;
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pciintr_icu_handle_t *phandp;
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{
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pcireg_t reg;
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if (piix_init(pc, iot, tag, ptagp, phandp) == 0) {
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*ptagp = &via82c586_pci_icu;
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/*
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* Enable EISA ELCR.
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*/
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reg = pci_conf_read(pc, tag, VP3_CFG_KBDMISCCTRL12_REG);
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reg |= VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE <<
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VP3_CFG_MISCCTRL2_SHIFT;
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pci_conf_write(pc, tag, VP3_CFG_KBDMISCCTRL12_REG, reg);
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return (0);
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}
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return (1);
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}
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int
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via82c586_getclink(v, link, clinkp)
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pciintr_icu_handle_t v;
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int link, *clinkp;
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{
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if (VP3_LEGAL_LINK(link - 1)) {
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*clinkp = link - 1;
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return (0);
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}
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return (1);
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}
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int
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via82c586_get_intr(v, clink, irqp)
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pciintr_icu_handle_t v;
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int clink, *irqp;
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{
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struct piix_handle *ph = v;
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pcireg_t reg;
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int val;
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if (VP3_LEGAL_LINK(clink) == 0)
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return (1);
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reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG);
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val = VP3_PIRQ(reg, clink);
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*irqp = (val == VP3_PIRQ_NONE) ?
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I386_PCI_INTERRUPT_LINE_NO_CONNECTION : val;
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return (0);
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}
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int
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via82c586_set_intr(v, clink, irq)
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pciintr_icu_handle_t v;
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int clink, irq;
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{
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struct piix_handle *ph = v;
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int shift, val;
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pcireg_t reg;
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if (VP3_LEGAL_LINK(clink) == 0 || VP3_LEGAL_IRQ(irq) == 0)
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return (1);
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reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG);
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via82c586_get_intr(v, clink, &val);
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shift = vp3_cfg_intr_shift[clink];
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reg &= ~(VP3_CFG_INTR_MASK << shift);
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reg |= (irq << shift);
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pci_conf_write(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG, reg);
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if (via82c586_get_intr(v, clink, &val) != 0 ||
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val != irq)
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return (1);
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return (0);
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}
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int
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via82c586_get_trigger(v, irq, triggerp)
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pciintr_icu_handle_t v;
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int irq, *triggerp;
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{
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struct piix_handle *ph = v;
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int i, error, check_consistency, pciirq, pcitrigger = IST_NONE;
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pcireg_t reg;
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if (VP3_LEGAL_IRQ(irq) == 0)
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return (1);
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check_consistency = 0;
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for (i = 0; i <= 3; i++) {
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via82c586_get_intr(v, i, &pciirq);
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if (pciirq == irq) {
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reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
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VP3_CFG_PIRQ_REG);
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if (VP3_TRIGGER(reg, i) == VP3_CFG_TRIGGER_EDGE)
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pcitrigger = IST_EDGE;
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else
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pcitrigger = IST_LEVEL;
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check_consistency = 1;
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break;
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}
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}
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error = piix_get_trigger(v, irq, triggerp);
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if (error == 0 && check_consistency && pcitrigger != *triggerp)
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return (1);
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return (error);
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}
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int
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via82c586_set_trigger(v, irq, trigger)
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pciintr_icu_handle_t v;
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int irq, trigger;
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{
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struct piix_handle *ph = v;
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int i, pciirq, shift, testtrig;
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pcireg_t reg;
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if (VP3_LEGAL_IRQ(irq) == 0)
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return (1);
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for (i = 0; i <= 3; i++) {
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via82c586_get_intr(v, i, &pciirq);
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if (pciirq == irq) {
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reg = pci_conf_read(ph->ph_pc, ph->ph_tag,
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VP3_CFG_PIRQ_REG);
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shift = vp3_cfg_trigger_shift[i];
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if (trigger == IST_LEVEL)
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reg &= ~(VP3_CFG_TRIGGER_MASK << shift);
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else
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reg |= (VP3_CFG_TRIGGER_EDGE << shift);
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pci_conf_write(ph->ph_pc, ph->ph_tag,
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VP3_CFG_PIRQ_REG, reg);
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break;
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}
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}
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if (piix_set_trigger(v, irq, trigger) != 0 ||
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via82c586_get_trigger(v, irq, &testtrig) != 0 ||
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testtrig != trigger)
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return (1);
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return (0);
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}
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