238 lines
6.5 KiB
C
238 lines
6.5 KiB
C
/* $NetBSD: e500_timer.c,v 1.4 2011/06/29 05:56:31 matt Exp $ */
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/*-
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* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
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* Agency and which was developed by Matt Thomas of 3am Software Foundry.
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*
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* This material is based upon work supported by the Defense Advanced Research
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* Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
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* Contract No. N66001-09-C-2073.
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* Approved for Public Release, Distribution Unlimited
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: e500_timer.c,v 1.4 2011/06/29 05:56:31 matt Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/timetc.h>
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#include <sys/intr.h>
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#include <sys/cpu.h>
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#include <uvm/uvm_extern.h>
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#include <powerpc/spr.h>
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#include <powerpc/booke/spr.h>
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#include <powerpc/booke/cpuvar.h>
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#include <powerpc/booke/e500reg.h>
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#include <powerpc/booke/e500var.h>
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#include <powerpc/booke/openpicreg.h>
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static u_long ns_per_tick;
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static void init_ppcbooke_tc(void);
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static u_int get_ppcbooke_timecount(struct timecounter *);
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static struct timecounter ppcbooke_timecounter = {
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get_ppcbooke_timecount, /* get_timecount */
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0, /* no poll_pps */
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~0u, /* counter_mask */
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0, /* frequency */
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"ppc_timebase", /* name */
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100, /* quality */
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NULL, /* tc_priv */
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NULL /* tc_next */
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};
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static inline uint32_t
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openpic_read(struct cpu_softc *cpu, bus_size_t offset)
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{
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return bus_space_read_4(cpu->cpu_bst, cpu->cpu_bsh,
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OPENPIC_BASE + offset);
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}
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static inline void
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openpic_write(struct cpu_softc *cpu, bus_size_t offset, uint32_t val)
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{
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return bus_space_write_4(cpu->cpu_bst, cpu->cpu_bsh,
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OPENPIC_BASE + offset, val);
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}
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int
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e500_clock_intr(void *v)
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{
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struct trapframe * const tf = v;
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struct cpu_info * const ci = curcpu();
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struct cpu_softc * const cpu = ci->ci_softc;
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u_int nticks;
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/*
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* Check whether we are initialized.
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*/
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if (!cpu->cpu_ticks_per_clock_intr)
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return 0;
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/*
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* Now let's how delayed the clock interrupt was. Obviously it must
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* at least one clock tick since the clock interrupt. But it might
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* be more if interrupts were blocked for a long time. We keep
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* suubtracting an interrupts We should be
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* [well] within a single tick.
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* We add back one tick (which should put us back above 0). If we
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* are still below 0, keep adding ticks until we are above 0.
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*/
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const uint64_t now = mftb();
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uint64_t latency = now - (ci->ci_lastintr + cpu->cpu_ticks_per_clock_intr);
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#if 0
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uint64_t orig_latency = latency;
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#endif
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if (now < ci->ci_lastintr + cpu->cpu_ticks_per_clock_intr)
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latency = 0;
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nticks = 1 + latency / cpu->cpu_ticks_per_clock_intr;
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latency %= cpu->cpu_ticks_per_clock_intr;
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#if 0
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for (nticks = 1; latency >= cpu->cpu_ticks_per_clock_intr; nticks++) {
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latency -= cpu->cpu_ticks_per_clock_intr;
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}
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#endif
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ci->ci_ev_clock.ev_count++;
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cpu->cpu_ev_late_clock.ev_count += nticks - 1;
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/*
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* lasttb is used during microtime. Set it to the virtual
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* start of this tick interval.
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*/
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#if 0
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if (nticks > 10 || now - ci->ci_lastintr < 7 * cpu->cpu_ticks_per_clock_intr / 8)
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printf("%s: nticks=%u lastintr=%#"PRIx64"(%#"PRIx64") now=%#"PRIx64" latency=%#"PRIx64" orig=%#"PRIx64"\n", __func__,
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nticks, ci->ci_lastintr, now - latency, now, latency, orig_latency);
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#endif
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ci->ci_lastintr = now - latency;
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ci->ci_lasttb = now;
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wrtee(PSL_EE); /* Reenable interrupts */
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/*
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* Do standard timer interrupt stuff.
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*/
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while (nticks-- > 0) {
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hardclock(&tf->tf_cf);
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}
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wrtee(0); /* turn off interrupts */
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tf->tf_srr1 &= ~PSL_POW; /* make cpu_idle exit */
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return 1;
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}
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void
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cpu_initclocks(void)
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{
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struct cpu_info * const ci = curcpu();
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struct cpu_softc * const cpu = ci->ci_softc;
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cpu->cpu_ticks_per_clock_intr = (ci->ci_data.cpu_cc_freq + hz/2 - 1) / hz;
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/* interrupt established in e500_intr_cpu_init */
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ci->ci_lastintr = ci->ci_lasttb = mftb();
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openpic_write(cpu, cpu->cpu_clock_gtbcr,
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GTBCR_CI | cpu->cpu_ticks_per_clock_intr);
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openpic_write(cpu, cpu->cpu_clock_gtbcr,
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cpu->cpu_ticks_per_clock_intr);
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if (CPU_IS_PRIMARY(ci))
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init_ppcbooke_tc();
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}
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void
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calc_delayconst(void)
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{
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struct cpu_info * const ci = curcpu();
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ci->ci_data.cpu_cc_freq = board_info_get_number("timebase-frequency");
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ns_per_tick = 1000000000 / (u_int)ci->ci_data.cpu_cc_freq;
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}
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static u_int
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get_ppcbooke_timecount(struct timecounter *tc)
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{
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return mftbl();
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}
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/*
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* Wait for about n microseconds (at least!).
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*/
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void
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delay(unsigned int n)
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{
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uint64_t tb;
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u_long tbh, tbl, scratch;
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tb = mftb();
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/* use 1000ULL to force 64 bit math to avoid 32 bit overflows */
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tb += (n * 1000ULL + ns_per_tick - 1) / ns_per_tick;
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tbh = tb >> 32;
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tbl = tb;
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__asm volatile (
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"1: mfspr %0,%4" "\n"
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" cmplw %0,%1" "\n"
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" blt 1b" "\n"
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" bgt 2f" "\n"
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" mfspr %0,%3" "\n"
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" cmplw %0,%2" "\n"
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" blt 1b" "\n"
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"2:" "\n"
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: "=&r"(scratch)
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: "r"(tbh), "r"(tbl), "n"(SPR_TBL), "n"(SPR_TBU)
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: "cr0");
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}
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/*
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* Nothing to do.
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*/
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void
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setstatclockrate(int arg)
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{
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/* Do nothing */
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}
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static void
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init_ppcbooke_tc(void)
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{
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/* from machdep initialization */
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ppcbooke_timecounter.tc_frequency = curcpu()->ci_data.cpu_cc_freq;
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tc_init(&ppcbooke_timecounter);
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}
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