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a12c.c
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Allow rd/line, rd/mult, and wr/inval.
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1999-11-04 19:15:22 +00:00 |
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a12c_bus_mem.c
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…
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a12c_dma.c
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…
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a12c_pci.c
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…
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a12creg.h
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…
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a12cvar.h
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Support attachment of xb and a12dc, define most of the remaining
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1998-03-02 06:56:16 +00:00 |
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apecs.c
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Allow rd/line, rd/mult, and wr/inval.
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1999-11-04 19:15:22 +00:00 |
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apecs_bus_io.c
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…
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apecs_bus_mem.c
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…
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apecs_dma.c
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…
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apecs_pci.c
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…
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apecsreg.h
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…
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apecsvar.h
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Treat bus space tags more like pci chipset tags and bus dma tags: allocate
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1997-09-02 12:40:18 +00:00 |
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cia.c
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Don't do rd/line, rd/mult, or wr/inval on the buggy Miata 1's.
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1999-11-04 19:11:51 +00:00 |
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cia_bwx_bus_io.c
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CIA core logic with BWX enabled appears on both EV56 and PCA56. We
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1999-12-02 19:43:25 +00:00 |
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cia_bwx_bus_mem.c
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CIA core logic with BWX enabled appears on both EV56 and PCA56. We
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1999-12-02 19:43:25 +00:00 |
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cia_dma.c
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Fix a fatal typo in a Pyxis SGMAP TLB bug workaround. Noticed by
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2000-01-25 03:32:36 +00:00 |
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cia_pci.c
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…
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cia_swiz_bus_io.c
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…
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cia_swiz_bus_mem.c
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…
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ciareg.h
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…
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ciavar.h
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Don't do rd/line, rd/mult, or wr/inval on the buggy Miata 1's.
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1999-11-04 19:11:51 +00:00 |
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dwlpx.c
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Allow rd/line, rd/mult, and wr/inval.
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1999-11-04 19:15:22 +00:00 |
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dwlpx_bus_io.c
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…
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dwlpx_bus_mem.c
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…
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dwlpx_dma.c
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…
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dwlpx_pci.c
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…
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dwlpxreg.h
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…
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dwlpxvar.h
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…
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lca.c
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Allow rd/line, rd/mult, and wr/inval.
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1999-11-04 19:15:22 +00:00 |
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lca_bus_io.c
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…
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lca_bus_mem.c
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…
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lca_dma.c
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…
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lca_pci.c
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…
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lcareg.h
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…
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lcavar.h
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…
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mcpcia.c
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Make sure a MCPCIA exists before trying to initialize it. Also make
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1999-11-16 18:33:11 +00:00 |
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mcpcia_bus_io.c
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…
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mcpcia_bus_mem.c
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…
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mcpcia_dma.c
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…
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mcpcia_pci.c
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…
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mcpciareg.h
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…
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mcpciavar.h
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…
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pci_550.c
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…
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pci_550.h
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…
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pci_1000.c
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Key off NSIO and NPCEB for (E)ISA interrupt support.
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1999-12-15 22:30:40 +00:00 |
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pci_1000.h
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…
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pci_1000a.c
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Key off NSIO and NPCEB for (E)ISA interrupt support.
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1999-12-15 22:31:04 +00:00 |
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pci_1000a.h
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…
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pci_2100_a50.c
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…
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pci_2100_a50.h
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…
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pci_6600.c
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…
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pci_6600.h
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…
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pci_a12.c
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…
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pci_a12.h
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…
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pci_alphabook1.c
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#include <machine/intrcnt.h>
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1998-11-19 02:35:39 +00:00 |
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pci_alphabook1.h
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Very preliminary support for the Tadpole/DEC AlphaBook. These are basically
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1998-06-26 05:42:34 +00:00 |
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pci_axppci_33.c
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…
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pci_axppci_33.h
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…
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pci_bwx_bus_io_chipdep.c
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Pull in the BWX inlines. We expect the arch to be set appropriately for
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1999-12-02 19:44:49 +00:00 |
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pci_bwx_bus_mem_chipdep.c
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Pull in the BWX inlines. We expect the arch to be set appropriately for
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1999-12-02 19:44:49 +00:00 |
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pci_eb64plus.c
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…
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pci_eb64plus.h
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…
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pci_eb64plus_intr.s
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…
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pci_eb66.c
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…
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pci_eb66.h
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Take a stab at EB66 support. An EB66 is basically an EB64+ with a
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1998-06-27 10:10:51 +00:00 |
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pci_eb66_intr.s
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…
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pci_eb164.c
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…
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pci_eb164.h
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…
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pci_eb164_intr.s
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…
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pci_kn8ae.c
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…
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pci_kn8ae.h
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…
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pci_kn20aa.c
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Key off NSIO and NPCEB for (E)ISA interrupt support.
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1999-12-15 22:28:15 +00:00 |
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pci_kn20aa.h
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…
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pci_kn300.c
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Key off NSIO and NPCEB for (E)ISA interrupt support.
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1999-12-15 22:25:21 +00:00 |
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pci_kn300.h
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add Alpha 4100 support
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1998-04-15 00:50:14 +00:00 |
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pci_machdep.c
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…
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pci_sgmap_pte32.c
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…
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pci_sgmap_pte32.h
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…
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pci_sgmap_pte64.c
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…
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pci_sgmap_pte64.h
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…
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pci_swiz_bus_io_chipdep.c
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Clarify what appear to the untrained eye to be two magic constants (the
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1999-12-07 05:44:57 +00:00 |
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pci_swiz_bus_mem_chipdep.c
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Handle the case where PCI dense memory and PCI sparse memory don't
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1999-12-08 01:48:39 +00:00 |
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pciide_machdep.c
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…
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sio.c
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recognise the ACER labs M1543 PCI-ISA Bridge in siomatch(). the DS10 now boots!
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1999-11-12 22:07:28 +00:00 |
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sio_pic.c
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Fix the 16-bytes-of-death bug by generating specific-EOI cycles during
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1999-07-30 20:33:43 +00:00 |
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sioreg.h
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…
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siovar.h
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…
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tsc.c
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Allow rd/line, rd/mult, and wr/inval.
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1999-11-04 19:15:22 +00:00 |
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tsp_bus_io.c
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CIA core logic with BWX enabled appears on EV6. We require at least
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1999-12-02 19:43:58 +00:00 |
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tsp_bus_mem.c
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CIA core logic with BWX enabled appears on EV6. We require at least
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1999-12-02 19:43:58 +00:00 |
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tsp_dma.c
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…
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tsp_pci.c
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…
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tsreg.h
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…
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tsvar.h
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…
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