86 lines
3.4 KiB
C
86 lines
3.4 KiB
C
/* $NetBSD: vraiureg.h,v 1.1 2002/03/23 09:02:02 hamajima Exp $ */
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/*
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* Copyright (c) 2001 HAMAJIMA Katsuomi. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* AIU (Audio Interface Unit) Registers definitions.
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*/
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#define MDMADAT_REG_W 0x000 /* Mic DMA Data Register (10bit) */
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#define SDMADAT_REG_W 0x002 /* Speaker DMA Data Register (10bit) */
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#define SODATA_REG_W 0x006 /* Speaker Output Data Register (10bit) */
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#define SCNT_REG_W 0x008 /* Speaker Control Register */
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#define DAENAIU (1<<15) /* D/A Enable */
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#define SSTATE (1<<3) /* Speaker Status */
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#define SSTOPEN (1<<1) /* Speaker Stop End
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(1: 1 page, 0: 2 page) */
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#define SCNVR_REG_W 0x00a /* Speaker Converter Rate Register */
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#define SPS8000 (4) /* 8k sps */
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#define SPS44100 (2) /* 44.1k sps */
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#define SPS22050 (1) /* 22.05k sps */
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#define SPS11025 (0) /* 11.025k sps */
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#define MIDAT_REG_W 0x010 /* Mic Input Data Register (10bit) */
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#define MCNT_REG_W 0x012 /* Mic Control Register */
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#define ADENAIU (1<<15) /* A/D Enable */
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#define MSTATE (1<<3) /* Mic Status */
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#define MSTOPEN (1<<1) /* Mic Stop End
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(1: 1 page, 0: 2 page) */
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#define ADREQAIU (1) /* A/D Request */
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#define MCNVR_REG_W 0x014 /* Mic Converter Rate Register */
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/* same SCNVR_REG_W(0x00a)
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#define SPS8000 (4)
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#define SPS44100 (2)
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#define SPS22050 (1)
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#define SPS11025 (0)
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*/
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#define DVALID_REG_W 0x018 /* Data Valid Register */
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#define SODATV (1<<3) /* SODATREG Valid */
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#define SOMAV (1<<2) /* SDMADATREG Valid */
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#define MIDATV (1<<1) /* MIDATREG Valid */
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#define MDMAV (1) /* MDMADATREG Valid */
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#define SEQ_REG_W 0x01a /* Sequencer Register */
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#define AIURST (1<<15) /* AIU Reset */
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#define AIUMEN (1<<4) /* Mic Enable */
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#define AIUSEN (1) /* Speaker Enable */
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#define INT_REG_W 0x01c /* Interrupt Register */
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#define MENDINTR (1<<11) /* Mic End Interrupt */
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#define MINTR (1<<10) /* Mic Interrupt */
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#define MIDLEINTR (1<<9) /* Mic Idle Interrupt */
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#define MSTINTR (1<<8) /* Mic Set Interrupt */
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#define SENDINTR (1<<3) /* Speaker End Interrupt */
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#define SINTR (1<<2) /* Speaker Interrupt */
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#define SIDLEINTR (1<<1) /* Speaker Idle Interrupt */
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