342 lines
7.0 KiB
ArmAsm
342 lines
7.0 KiB
ArmAsm
/* $NetBSD: isa_io_asm.S,v 1.3 1998/09/05 01:31:53 mark Exp $ */
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/*-
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* Copyright (c) 1997 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Mark Brinicombe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright 1997
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* Digital Equipment Corporation. All rights reserved.
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*
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* This software is furnished under license and may be used and
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* copied only in accordance with the following terms and conditions.
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* Subject to these conditions, you may download, copy, install,
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* use, modify and distribute this software in source and/or binary
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* form. No title or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce
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* and retain this copyright notice and list of conditions as
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* they appear in the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or logo of
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* Digital Equipment Corporation. Neither the "Digital Equipment
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* Corporation" name nor any trademark or logo of Digital Equipment
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* Corporation may be used to endorse or promote products derived
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* from this software without the prior written permission of
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* Digital Equipment Corporation.
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*
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* 3) This software is provided "AS-IS" and any express or implied
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* warranties, including but not limited to, any implied warranties
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* of merchantability, fitness for a particular purpose, or
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* non-infringement are disclaimed. In no event shall DIGITAL be
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* liable for any damages whatsoever, and in particular, DIGITAL
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* shall not be liable for special, indirect, consequential, or
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* incidental damages or damages for lost profits, loss of
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* revenue or loss of use, whether such damages arise in contract,
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* negligence, tort, under statute, in equity, at law or otherwise,
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* even if advised of the possibility of such damage.
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*/
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/*
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* bus_space I/O functions for isa
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*/
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#include <machine/asm.h>
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#ifdef GPROF
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#define PAUSE nop ; nop ; nop ; nop ; nop
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#else
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#define PAUSE
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#endif
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/*
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* Note these functions use ARM Architecture V4 instructions as
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* all current systems with ISA will be using processors that support
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* V4 or later architectures (SHARK & CATS)
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*/
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/*
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* read single
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*/
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ENTRY(isa_bs_r_1)
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ldrb r0, [r1, r2]
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PAUSE
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mov pc, lr
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ENTRY(isa_bs_r_2)
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ldrh r0, [r1, r2] /*.word 0xe19100b2*/
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PAUSE
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mov pc, lr
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ENTRY(isa_bs_r_4)
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ldr r0, [r1, r2]
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PAUSE
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mov pc, lr
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/*
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* read multiple.
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*/
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ENTRY(isa_bs_rm_1)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_rm_1_loop:
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ldrb r3, [r0]
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strb r3, [r1], #1
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subs r2, r2, #1
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bne Lisa_rm_1_loop
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mov pc, lr
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ENTRY(isa_bs_rm_2)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_rm_2_loop:
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ldrh r3, [r0] /*.word 0xe1d030b0*/
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strh r3, [r1], #2 /*.word 0xe0c130b2*/
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subs r2, r2, #1
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bne Lisa_rm_2_loop
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mov pc, lr
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ENTRY(isa_bs_rm_4)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_rm_4_loop:
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ldr r3, [r0]
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str r3, [r1], #4
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subs r2, r2, #1
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bne Lisa_rm_4_loop
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mov pc, lr
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/*
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* read region.
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*/
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ENTRY(isa_bs_rr_1)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_rr_1_loop:
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ldrb r3, [r0], #1
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strb r3, [r1], #1
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subs r2, r2, #1
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bne Lisa_rr_1_loop
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mov pc, lr
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ENTRY(isa_bs_rr_2)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_rr_2_loop:
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ldrh r3, [r0], #2
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strh r3, [r1], #2 /*.word 0xe0c130b2*/
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subs r2, r2, #1
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bne Lisa_rr_2_loop
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mov pc, lr
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ENTRY(isa_bs_rr_4)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_rr_4_loop:
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ldr r3, [r0], #4
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str r3, [r1], #4
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subs r2, r2, #1
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bne Lisa_rr_4_loop
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mov pc, lr
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/*
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* write single
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*/
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ENTRY(isa_bs_w_1)
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strb r3, [r1, r2]
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PAUSE
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mov pc, lr
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ENTRY(isa_bs_w_2)
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strh r3, [r1, r2] /*.word 0xe18130b2*/
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PAUSE
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mov pc, lr
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ENTRY(isa_bs_w_4)
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str r3, [r1, r2]
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PAUSE
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mov pc, lr
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/*
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* write multiple
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*/
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ENTRY(isa_bs_wm_1)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_wm_1_loop:
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ldrb r3, [r1], #1
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strb r3, [r0]
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subs r2, r2, #1
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bne Lisa_wm_1_loop
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mov pc, lr
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ENTRY(isa_bs_wm_2)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_wm_2_loop:
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ldrh r3, [r1], #2 /*.word 0xe0d130b2*/
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strh r3, [r0] /*.word 0xe1c030b0*/
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subs r2, r2, #1
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bne Lisa_wm_2_loop
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mov pc, lr
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ENTRY(isa_bs_wm_4)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_wm_4_loop:
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ldr r3, [r1], #4
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str r3, [r0]
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subs r2, r2, #1
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bne Lisa_wm_4_loop
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mov pc, lr
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/*
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* write region.
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*/
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ENTRY(isa_bs_wr_1)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_wr_1_loop:
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ldrb r3, [r1], #1
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strb r3, [r0], #1
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subs r2, r2, #1
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bne Lisa_wr_1_loop
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mov pc, lr
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ENTRY(isa_bs_wr_2)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_wr_2_loop:
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ldrh r3, [r1], #2 /*.word 0xe0d130b2*/
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strh r3, [r0], #2
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subs r2, r2, #1
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bne Lisa_wr_2_loop
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mov pc, lr
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ENTRY(isa_bs_wr_4)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_wr_4_loop:
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ldr r3, [r1], #4
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str r3, [r0], #4
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subs r2, r2, #1
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bne Lisa_wr_4_loop
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mov pc, lr
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/*
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* Set region
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*/
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ENTRY(isa_bs_sr_2)
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add r0, r1, r2
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mov r1, r3
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ldr r2, [sp, #0]
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teq r2, #0
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moveq pc, lr
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Lisa_bs_sr_2_loop:
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strh r1, [r0], #2 /*.word e0c010b2*/
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subs r2, r2, #1
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bne Lisa_bs_sr_2_loop
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mov pc, lr
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