242 lines
8.2 KiB
C
242 lines
8.2 KiB
C
/* $NetBSD: mmureg.h,v 1.6 2002/02/11 18:03:48 uch Exp $ */
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/*-
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* Copyright (C) 2002 UCHIYAMA Yasushi. All rights reserved.
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* Copyright (C) 1999 SAITOH Masanobu. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH3_MMUREG_H__
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#define _SH3_MMUREG_H__
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#ifdef _KERNEL
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/*
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* MMU
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*/
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#if !defined(SH4)
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/* SH3 definitions */
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#define SHREG_PTEH (*(volatile unsigned long *) 0xFFFFFFF0)
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#define SHREG_PTEL (*(volatile unsigned long *) 0xFFFFFFF4)
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#define SHREG_TTB (*(volatile unsigned long *) 0xFFFFFFF8)
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#define SHREG_TEA (*(volatile unsigned long *) 0xFFFFFFFC)
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#define SHREG_MMUCR (*(volatile unsigned long *) 0xFFFFFFE0)
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#else /* !SH4 */
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/* SH4 definitions */
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#define SHREG_PTEH (*(volatile unsigned long *) 0xff000000)
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#define SHREG_PTEL (*(volatile unsigned long *) 0xff000004)
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#define SHREG_PTEA (*(volatile unsigned long *) 0xff000034)
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#define SHREG_TTB (*(volatile unsigned long *) 0xff000008)
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#define SHREG_TEA (*(volatile unsigned long *) 0xff00000c)
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#define SHREG_MMUCR (*(volatile unsigned long *) 0xff000010)
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#endif /* !SH4 */
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#if !defined(SH4)
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/* SH3 definitions */
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#define MMUCR_AT 0x0001 /* address traslation enable */
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#define MMUCR_IX 0x0002 /* index mode */
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#define MMUCR_TF 0x0004 /* TLB flush */
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#define MMUCR_SV 0x0100 /* single virtual space mode */
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#else /* !SH4 */
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/* SH4 definitions */
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#define MMUCR_AT 0x0001 /* address traslation enable */
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#define MMUCR_TI 0x0004 /* TLB Invaliate */
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#define MMUCR_SV 0x0100 /* single virtual space mode */
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#define MMUCR_SQMD 0x0200 /* Store Queue mode */
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#define MMUCR_VALIDBITS 0xfcfcff05 /* XXX */
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/* alias */
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#define MMUCR_TF MMUCR_TI
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#endif /* !SH4 */
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extern int PageDirReg;
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/*
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* name-space free version.
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*/
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/*
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* SH3
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*/
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/* 128-entry 4-way set-associative */
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#define SH3_MMU_WAY 4
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#define SH3_MMU_ENTRY 32
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#define SH3_PTEH 0xfffffff0
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#define SH3_PTEH_ASID_MASK 0x0000000f
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#define SH3_PTEH_VPN_MASK 0xfffffc00
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#define SH3_PTEL 0xfffffff4
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#define SH3_PTEL_HWBITS 0x1ffff17e /* [28:12][8][6:1] */
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#define SH3_TTB 0xfffffff8
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#define SH3_TEA 0xfffffffc
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#define SH3_MMUCR 0xffffffe0
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#define SH3_MMUCR_AT 0x00000001
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#define SH3_MMUCR_IX 0x00000002
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#define SH3_MMUCR_TF 0x00000004
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#define SH3_MMUCR_RC 0x00000030
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#define SH3_MMUCR_SV 0x00000100
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/*
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* memory-mapped TLB
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*/
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/* Address array */
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#define SH3_MMUAA 0xf2000000
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/* address specification */
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#define SH3_MMU_VPN_SHIFT 12
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#define SH3_MMU_VPN_MASK 0x0001f000 /* [16:12] */
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#define SH3_MMU_WAY_SHIFT 8
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#define SH3_MMU_WAY_MASK 0x00000300
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/* data specification */
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#define SH3_MMU_D_VALID 0x00000100
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#define SH3_MMUAA_D_VPN_MASK 0xfffe0c00 /* [31:17][11:10] */
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#define SH3_MMUAA_D_ASID_MASK 0x0000000f
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/* Data array */
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#define SH3_MMUDA 0xf3000000
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#define SH3_MMUDA_D_PPN_MASK 0xfffffc00
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#define SH3_MMUDA_D_V 0x00000100
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#define SH3_MMUDA_D_PR_SHIFT 5
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#define SH3_MMUDA_D_PR_MASK 0x00000060 /* [6:5] */
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#define SH3_MMUDA_D_SZ 0x00000010
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#define SH3_MMUDA_D_C 0x00000008
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#define SH3_MMUDA_D_D 0x00000004
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#define SH3_MMUDA_D_SH 0x00000002
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/*
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* SH4
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*/
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/* ITLB 4-entry full-associative UTLB 64-entry full-associative */
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#define SH4_PTEH 0xff000000
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#define SH4_PTEH_ASID_MASK 0x0000000f
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#define SH4_PTEL 0xff000004
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#define SH4_PTEL_WT 0x00000001
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#define SH4_PTEL_SH 0x00000002
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#define SH4_PTEL_D 0x00000004
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#define SH4_PTEL_C 0x00000008
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#define SH4_PTEL_PR_SHIFT 5
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#define SH4_PTEL_PR_MASK 0x00000060 /* [5:6] */
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#define SH4_PTEL_SZ_MASK 0x00000090 /* [4][7] */
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#define SH4_PTEL_SZ_1K 0x00000000
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#define SH4_PTEL_SZ_4K 0x00000010
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#define SH4_PTEL_SZ_64K 0x00000080
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#define SH4_PTEL_SZ_1M 0x00000090
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#define SH4_PTEL_V 0x00000100
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#define SH4_PTEL_HWBITS 0x1ffff1ff /* [28:12]PFN [8:0]attr. */
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#define SH4_PTEA 0xff000034
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#define SH4_PTEA_SA_MASK 0x00000007
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#define SH4_PTEA_SA_TC 0x00000008
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#define SH4_TTB 0xff000008
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#define SH4_TTA 0xff00000c
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#define SH4_MMUCR 0xff000010
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#define SH4_MMUCR_AT 0x00000001
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#define SH4_MMUCR_TI 0x00000004
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#define SH4_MMUCR_SV 0x00000100
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#define SH4_MMUCR_SQMD 0x00000200
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#define SH4_MMUCR_URC_SHIFT 10
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#define SH4_MMUCR_URC_MASK 0x0000fc00 /* [10:15] */
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#define SH4_MMUCR_URB_SHIFT 18
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#define SH4_MMUCR_URB_MASK 0x00fc0000 /* [18:23] */
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#define SH4_MMUCR_LRUI_SHIFT 26
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#define SH4_MMUCR_LRUT_MASK 0xfc000000 /* [26:31] */
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/*
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* memory-mapped TLB
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* must be access from P2-area program.
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* branch to the other area must be maed at least 8 instruction
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* after access.
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*/
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/* ITLB */
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#define SH4_ITLB_AA 0xf2000000
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/* address specification (common for address and data array(0,1)) */
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#define SH4_ITLB_E_SHIFT 8
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#define SH4_ITLB_E_MASK 0x00000300 /* [9:8] */
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/* data specification */
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/* address-array */
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#define SH4_ITLB_AA_ASID_MASK 0x000000ff /* [7:0] */
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#define SH4_ITLB_AA_V 0x00000100
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#define SH4_ITLB_AA_VPN_SHIFT 10
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#define SH4_ITLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */
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/* data-array 1 */
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#define SH4_ITLB_DA1 0xf3000000
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#define SH4_ITLB_DA1_SH 0x00000002
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#define SH4_ITLB_DA1_C 0x00000008
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#define SH4_ITLB_DA1_SZ_MASK 0x00000090 /* [7][4] */
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#define SH4_ITLB_DA1_SZ_1K 0x00000000
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#define SH4_ITLB_DA1_SZ_4K 0x00000010
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#define SH4_ITLB_DA1_SZ_64K 0x00000080
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#define SH4_ITLB_DA1_SZ_1M 0x00000090
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#define SH4_ITLB_DA1_PR 0x00000040
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#define SH4_ITLB_DA1_V 0x00000100
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#define SH4_ITLB_DA1_PPN_SHIFT 11
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#define SH4_ITLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */
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/* data-array 2 */
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#define SH4_ITLB_DA2 0xf3800000
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#define SH4_ITLB_DA2_SA_MASK 0x00000003
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#define SH4_ITLB_DA2_TC 0x00000004
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/* UTLB */
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#define SH4_UTLB_AA 0xf6000000
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/* address specification (common for address and data array(0,1)) */
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#define SH4_UTLB_E_SHIFT 8
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#define SH4_UTLB_E_MASK 0x00003f00
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/* data specification */
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/* address-array */
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#define SH4_UTLB_AA_VPN_MASK 0xfffffc00 /* [31:10] */
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#define SH4_UTLB_AA_D 0x00000200
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#define SH4_UTLB_AA_V 0x00000100
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#define SH4_UTLB_AA_ASID_MASK 0x000000ff /* [7:0] */
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/* data-array 1 */
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#define SH4_UTLB_DA1 0xf7000000
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#define SH4_UTLB_DA1_WT 0x00000001
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#define SH4_UTLB_DA1_SH 0x00000002
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#define SH4_UTLB_DA1_D 0x00000004
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#define SH4_UTLB_DA1_C 0x00000008
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#define SH4_UTLB_DA1_SZ_MASK 0x00000090 /* [7][4] */
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#define SH4_UTLB_DA1_SZ_1K 0x00000000
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#define SH4_UTLB_DA1_SZ_4K 0x00000010
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#define SH4_UTLB_DA1_SZ_64K 0x00000080
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#define SH4_UTLB_DA1_SZ_1M 0x00000090
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#define SH4_UTLB_DA1_PR_SHIFT 5
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#define SH4_UTLB_DA1_PR_MASK 0x00000060
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#define SH4_UTLB_DA1_V 0x00000100
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#define SH4_UTLB_DA1_PPN_SHIFT 11
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#define SH4_UTLB_DA1_PPN_MASK 0x1ffffc00 /* [28:10] */
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/* data-array 2 */
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#define SH4_UTLB_DA2 0xf7800000
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#define SH4_UTLB_DA2_SA_MASK 0x00000003
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#define SH4_UTLB_DA2_TC 0x00000004
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#endif /* _KERNEL */
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#endif /* !_SH3_MMUREG_H__ */
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