NetBSD/dist/ntp/html/driver30.htm

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<TITLE>Motorola Oncore GPS Receiver
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<H3>
Motorola Oncore GPS receiver</H3>
<HR>
<H4>
Synopsis</H4>
Address: 127.127.30.0<BR>
Reference ID: <TT>GPS</TT><BR>
Driver ID: ONCORE<BR>
Serial Port: <TT>/dev/oncore.serial.0</TT>; &nbsp;9600 baud, 8-bits,
no parity.<BR>
PPS Port: <TT>/dev/oncore.pps.0</TT>;&nbsp; <TT>PPS_CAPTUREASSERT</TT>
required,&nbsp; <TT>PPS_OFFSETASSERT</TT> supported.
<H4>
Description</H4>
This driver supports various models of the <A
HREF="http://www.mot.com/AECS/PNSB/products">Motorola Oncore GPS
receivers</A> as long as they support the <I>Motorola Binary
Protocol</I>.
<P>The three most interesting versions of the Oncore are the "VP",&nbsp;
the "UT+",&nbsp;
and the "Remote" which is a prepackaged "UT+".&nbsp;
The "VP" is no longer available.
The evaluation kit
can also be recommended, it interfaces to a PC straightaway, using the
serial (DCD) or parallel port for PPS input and packs the
receiver in a nice and sturdy box.
Two less expensive interface kits are available from
<A HREF="http://www.tapr.org">TAPR </A>.
<P>The driver requires a standard <TT>PPS</TT> interface for the
pulse-per-second output from the receiver.&nbsp; The serial data stream alone
does not provide precision time stamps (0-50msec variance, according to
the manual), whereas the PPS output is precise down to 50 nsec (1 sigma)
for the VP/UT models.
<P>The driver will use the "position hold" mode with
user provided coordinates,
the receivers built-in site-survey,
or a similar algorithm implemented in this driver to determine the antenna position.
<H4>
Monitor Data</H4>
The driver is quite chatty on stdout if ntpd is run with debugging.
<P>
In addition, on platforms supporting Shared Memory, all of the messages
received from the Oncore receiver are made available in shared memory for
use by other programs.
See the <A HREF=Oncore-SHMEM.htm> Oncore-SHMEM </A> manual page for
information on how to use this option.
For either debugging or using the SHMEM option, an Oncore Reference Manual
for the specific receiver in use will be required.
<H4>
Fudge Factors</H4>
<DL>
<DT>
<TT>time1 <I>time</I></TT></DT>
<DD>
Specifies the time offset calibration factor, in seconds and fraction,
with default 0.0.</DD>
<DT>
<TT>time2 <I>time</I></TT></DT>
<DD>
Not used by this driver.</DD>
<DT>
<TT>stratum <I>number</I></TT></DT>
<DD>
Specifies the driver stratum, in decimal from 0 to 15, with default
0.</DD>
<DT>
<TT>refid <I>string</I></TT></DT>
<DD>
Specifies the driver reference identifier, an ASCII string from one to
four characters, with default <TT>GPS</TT>.</DD>
<DT>
<TT>flag1 0 | 1</TT></DT>
<DD>
Not used by this driver.</DD>
<DT>
<TT>flag2 0 | 1</TT></DT>
<DD>
Not used by this driver.</DD>
<DT>
<TT>flag3 0 | 1</TT></DT>
<DD>
Not used by this driver.</DD>
<DT>
<TT>flag4 0 | 1</TT></DT>
<DD>
Not used by this driver.</DD>
</DL>
<B>Additional Information</B>
<P>The driver was initially developed on FreeBSD, and has since been tested
on Linux, SunOS and Solaris.
<P>There is a driver specific configuration file <TT>/etc/ntp.oncore</TT>
that contains information on the startup mode, the location of the GPS
receiver, an offset of the PPS signal from zero, and the cable delay.
The offset shifts the PPS signal to avoid interrupt pileups `on' the second,
and adjust the timestamp accordingly.
See the driver source for information on this file.
The default with no file is: no delay, no offset, and a site survey is done
to get the location of the gps receiver.
<P>The <TT>/etc/ntp.conf</TT> file will need a line of the form<BR>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
<TT> pps /dev/oncore.pps.0 [ assert/clear ] hardpps</TT><BR>
if you want the oncore driver to control the kernel PLL.
For more information, see the <A HREF=clockopt.htm>Reference Clock
Options</A> page.
<P><B>Performance</B>
<P>Really good.&nbsp; With the VP/UT+, the generated PPS pulse is referenced
to UTC(GPS)&nbsp;with better than 50 nsec (1 sigma) accuracy.&nbsp; The
limiting factor will be the timebase of the computer and the precision
with which you can timestamp the rising flank of the
PPS&nbsp;signal.&nbsp;
Using FreeBSD,&nbsp; a FPGA&nbsp;based Timecounter/PPS&nbsp;interface
and an ovenized quartz oscillator, that performance has been reproduced.
&nbsp;For more details on this aspect:&nbsp; <A
HREF="http://phk.freebsd.dk/rover.html">Sub-Microsecond
timekeeping under FreeBSD</A>
<HR>
<ADDRESS>
Poul-Henning Kamp (phk@FreeBSD.org),
Reg Clemens (reg@dwf.com)
</ADDRESS>
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