130 lines
5.2 KiB
C
130 lines
5.2 KiB
C
/* $NetBSD: timerreg.h,v 1.6 1996/10/28 00:20:32 abrown Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)timerreg.h 8.1 (Berkeley) 6/11/93
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*/
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/*
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* Sun-4c counter/timer registers. The timers are implemented within
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* the cache chip (!). The counter and limit fields below could be
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* defined as:
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*
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* struct {
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* u_int t_limit:1, // limit reached
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* t_usec:21, // counter value in microseconds
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* t_mbz:10; // always zero
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* };
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*
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* but this is more trouble than it is worth.
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*
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* These timers work in a rather peculiar fashion. Most clock counters
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* run to 0 (as, e.g., on the VAX, where the ICR counts up to 0 from a
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* large unsigned number). On the Sun-4c, it counts up to a limit. But
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* for some reason, when it reaches the limit, it resets to 1, not 0.
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* Thus, if the limit is set to 4, the counter counts like this:
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*
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* 1, 2, 3, 1, 2, 3, ...
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*
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* and if we want to divide by N we must set the limit register to N+1.
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*
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* Sun-4m counters/timer registers are similar, with these exceptions:
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*
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* - the limit and counter registers have changed positions..
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* - both limit and counter registers are 22 bits wide, but
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* they count in 500ns increments (bit 9 being the least
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* significant bit).
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*
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*/
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#ifndef _LOCORE
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struct timer_4 {
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volatile int t_counter; /* counter reg */
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volatile int t_limit; /* limit reg */
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};
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struct timerreg_4 {
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struct timer_4 t_c10; /* counter that interrupts at ipl 10 */
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struct timer_4 t_c14; /* counter that interrupts at ipl 14 */
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};
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struct timer_4m { /* counter that interrupts at ipl 10 */
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volatile int t_limit; /* limit register */
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volatile int t_counter; /* counter register */
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volatile int t_limit_nr; /* limit reg, non-resetting */
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volatile int t_reserved;
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volatile int t_cfg; /* a configuration register */
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/*
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* Note: The SparcClassic manual only defines this one bit
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* I suspect there are more in multi-processor machines.
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*/
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#define TMR_CFG_USER 1
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};
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struct counter_4m { /* counter that interrupts at ipl 14 */
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volatile int t_limit; /* limit register */
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volatile int t_counter; /* counter register */
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volatile int t_limit_nr; /* limit reg, non-resetting */
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volatile int t_ss; /* Start/Stop register */
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#define TMR_USER_RUN 1
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};
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#endif /* _LOCORE */
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#define TMR_LIMIT 0x80000000 /* counter reached its limit */
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#define TMR_SHIFT 10 /* shift to obtain microseconds */
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#define TMR_MASK 0x1fffff /* 21 bits */
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/*
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* Compute a limit that causes the timer to fire every n microseconds.
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* The Sun4c requires that the timer register be initialized for n+1
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* microseconds, while the Sun4m requires it be initialized for n. Thus
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* the two versions of this function.
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*
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* Note that the manual for the chipset used in the Sun4m suggests that
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* the timer be set at n+0.5 microseconds; in practice, this produces
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* a 50 ppm clock skew, which means that the 0.5 should not be there...
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*/
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#define tmr_ustolim(n) (((n) + 1) << TMR_SHIFT)
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/*efine TMR_SHIFT4M 9 -* shift to obtain microseconds */
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/*efine tmr_ustolim4m(n) (((2*(n)) + 1) << TMR_SHIFT4M)*/
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#define tmr_ustolim4m(n) ((n) << TMR_SHIFT)
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