145 lines
5.2 KiB
C
145 lines
5.2 KiB
C
/* $NetBSD: ka820.h,v 1.6 2003/08/07 16:30:10 agc Exp $ */
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/*
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* Copyright (c) 1988 Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Chris Torek.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ka820.h 7.3 (Berkeley) 6/28/90
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*/
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/*
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* Definitions specific to the ka820 cpu.
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*/
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#ifndef _VAX_KA820_H_
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#define _VAX_KA820_H_
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/*
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* Device addresses.
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*/
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#define KA820_PORTADDR 0x20088000 /* port controller */
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#define KA820_BRAMADDR 0x20090000 /* boot ram */
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#define KA820_EEPROMADDR 0x20098000 /* eeprom */
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#define KA820_RX50ADDR 0x200b0000 /* rcx50 */
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#define KA820_CLOCKADDR 0x200b8000 /* watch chip */
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/*
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* Sizes. The port controller, RCX50, and watch chip are all one page.
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*/
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#define KA820_BRPAGES 16 /* 8K */
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#define KA820_EEPAGES 64 /* 32K */
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/* port controller CSR bit values */
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#define KA820PORT_RSTHALT 0x80000000 /* restart halt */
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#define KA820PORT_LCONS 0x40000000 /* logical console */
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#define KA820PORT_LCONSEN 0x20000000 /* logical console enable */
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#define KA820PORT_BIRESET 0x10000000 /* BI reset */
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#define KA820PORT_BISTF 0x08000000 /* ??? */
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#define KA820PORT_ENBAPT 0x04000000 /* ??? */
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#define KA820PORT_STPASS 0x02000000 /* self test pass */
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#define KA820PORT_RUN 0x01000000 /* run */
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#define KA820PORT_WWPE 0x00800000 /* ??? parity even? */
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#define KA820PORT_EVLCK 0x00400000 /* event lock */
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#define KA820PORT_WMEM 0x00200000 /* write mem */
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#define KA820PORT_EV4 0x00100000 /* event 4 */
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#define KA820PORT_EV3 0x00080000 /* event 3 */
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#define KA820PORT_EV2 0x00040000 /* event 2 */
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#define KA820PORT_EV1 0x00020000 /* event 1 */
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#define KA820PORT_EV0 0x00010000 /* event 0 */
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#define KA820PORT_WWPO 0x00008000 /* ??? parity odd? */
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#define KA820PORT_PERH 0x00004000 /* parity error H */
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#define KA820PORT_ENBPIPE 0x00002000 /* enable? pipe */
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#define KA820PORT_TIMEOUT 0x00001000 /* timeout */
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#define KA820PORT_RSVD 0x00000800 /* reserved */
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#define KA820PORT_CONSEN 0x00000400 /* console interrupt enable */
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#define KA820PORT_CONSCLR 0x00000200 /* clear console interrupt */
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#define KA820PORT_CONSINTR 0x00000100 /* console interrupt req */
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#define KA820PORT_RXIE 0x00000080 /* RX50 interrupt enable */
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#define KA820PORT_RXCLR 0x00000040 /* clear RX50 interrupt */
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#define KA820PORT_RXIRQ 0x00000020 /* RX50 interrupt request */
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#define KA820PORT_IPCLR 0x00000010 /* clear IP interrupt */
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#define KA820PORT_IPINTR 0x00000008 /* IP interrupt request */
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#define KA820PORT_CRDEN 0x00000004 /* enable CRD interrupts */
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#define KA820PORT_CRDCLR 0x00000002 /* clear CRD interrupt */
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#define KA820PORT_CRDINTR 0x00000001 /* CRD interrupt request */
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/* interrupt vectors unique for this CPU */
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#define KA820_INT_RXCD 0x58
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#define KA820_INT_IPINTR 0x80
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/* what the heck */
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#define KA820PORT_BITS \
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"\20\40RSTHALT\37LCONS\36LCONSEN\35BIRESET\34BISTF\33ENBAPT\32STPASS\31RUN\
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\30WWPE\27EVLCK\26WMEM\25EV4\24EV3\23EV2\22EV1\21EV\20WWPO\17PERH\16ENBPIPE\
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\15TIMEOUT\13CONSEN\12CONSCLR\11CONSINTR\10RXIE\7RXCLR\6RXIRQ\5IPCLR\4IPINTR\
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\3CRDEN\2CLRCLR\1CRDINTR"
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/* clock CSR bit values, per csr */
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#define KA820CLK_0_BUSY 0x01 /* busy (time changing) */
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#define KA820CLK_1_GO 0x0c /* run */
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#define KA820CLK_1_SET 0x0d /* set the time */
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#define KA820CLK_3_VALID 0x01 /* clock is valid */
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#ifndef LOCORE
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struct ka820port {
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u_long csr;
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/* that seems to be all.... */
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};
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struct ka820clock {
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u_char sec;
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u_char pad0;
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u_char secalrm;
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u_char pad1;
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u_char min;
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u_char pad2;
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u_char minalrm;
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u_char pad3;
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u_char hr;
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u_char pad4;
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u_char hralrm;
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u_char pad5;
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u_char dayofwk;
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u_char pad6;
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u_char day;
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u_char pad7;
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u_char mon;
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u_char pad8;
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u_char yr;
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u_char pad9;
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u_short csr0;
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u_short csr1;
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u_short csr2;
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u_short csr3;
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};
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void crxintr __P((void *arg));
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#endif /* _LOCORE */
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#endif /* _VAX_KA820_H_ */
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