97 lines
3.3 KiB
C
97 lines
3.3 KiB
C
/*
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* Copyright (c) 2001, 2002 Greg Hughes. All rights reserved.
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* Copyright (c) 1999 PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* DSIU (debug serial interface unit) register definitions
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*/
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/* Port Change Register */
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#define DSIUPORT_REG_W 0x00
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#define DSIUPORT_CDDIN (1 << 3)
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#define DSIUPORT_CDDOUT (1 << 2)
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#define DSIUPORT_CDRTS (1 << 1)
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#define DSIUPORT_CDCTS (1 << 0)
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/* Modem Control Register */
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#define DSIUMODEM_REG_W 0x02
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#define DSIUMODEM_DRTS (1 << 1)
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#define DSIUMODEM_DCTS (1 << 0)
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/* Asynchronous Mode 0 Register */
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#define DSIUASIM00_REG_W 0x04
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#define DSIUASIM00_RXE0 (1 << 6)
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#define DSIUASIM00_PS0_MASK (3 << 4)
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#define DSIUASIM00_PS00 (1 << 4)
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#define DSIUASIM00_PS01 (1 << 5)
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#define DSIUASIM00_CL0 (1 << 3)
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#define DSIUASIM00_SL0 (1 << 2)
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/* Asynchronous Mode 1 Register */
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#define DSIUASIM01_REG_W 0x06
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#define DSIUASIM01_EBS0 (1 << 0)
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/* Recceive Buffer Register (Extended) */
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#define DSIURXB0R_REG_W 0x08
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#define DSIURXB0R_RXB0_MASK (0x1FF << 0)
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/* Receive Buffer Register */
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#define DSIURXB0L_REG_W 0x0A
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#define DSIURXB0L_RXB0L_MASK (0xFF << 0)
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/* Transmit Data Register (Extended) */
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#define DSIUTXS0R_REG_W 0x0C
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#define DSIUTXS0R_TXS0_MASK (0x1FF << 0)
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/* Transmit Data Register */
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#define DSIUTXS0L_REG_W 0x0E
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#define DSIUTXS0L_TXS0L_MASK (0xFF << 0)
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/* Status Register */
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#define DSIUASIS0_REG_W 0x10
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#define DSIUASIS0_SOT0 (1 << 7)
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#define DSIUASIS0_PE0 (1 << 2)
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#define DSIUASIS0_FE0 (1 << 1)
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#define DSIUASIS0_OVE0 (1 << 0)
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/* Debug SIU Interrupt Register */
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#define DSIUINTR0_REG_W 0x12
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#define DSIUINTR0_INTDCD (1 << 3)
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#define DSIUINTR0_INTSER0 (1 << 2)
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#define DSIUINTR0_INTSR0 (1 << 1)
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#define DSIUINTR0_INTST0 (1 << 0)
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/* Baud rate Generator Prescaler Mode Register */
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#define DSIUBPRM0_REG_W 0x16
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#define DSIUBPRM0_BRCE0 (1 << 7)
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#define DSIUBPRM0_BPR0_MASK (7 << 0)
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#define DSIUBPRM0_BPR00 (1 << 0)
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#define DSIUBPRM0_BPR01 (1 << 1)
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#define DSIUBPRM0_BPR02 (1 << 2)
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/* Debug SIU Reset Register */
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#define DSIURESET_REG_W 0x18
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#define DSIURESET_DSIURST (1 << 0)
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