182 lines
4.9 KiB
C
182 lines
4.9 KiB
C
/* $NetBSD: pxa2x0_intr.h,v 1.4 2003/07/05 06:53:08 dogcow Exp $ */
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/* Derived from i80321_intr.h */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _PXA2X0_INTR_H_
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#define _PXA2X0_INTR_H_
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#define ARM_IRQ_HANDLER _C_LABEL(pxa2x0_irq_handler)
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#ifndef _LOCORE
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#include <arm/cpu.h>
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#include <arm/armreg.h>
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#include <arm/cpufunc.h>
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#include <machine/atomic.h>
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#include <machine/intr.h>
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#include <arm/softintr.h>
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#include <arm/xscale/pxa2x0reg.h>
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vaddr_t pxaic_base; /* Shared with pxa2x0_irq.S */
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#define read_icu(offset) (*(volatile uint32_t *)(pxaic_base+(offset)))
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#define write_icu(offset,value) \
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(*(volatile uint32_t *)(pxaic_base+(offset))=(value))
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extern __volatile int current_spl_level;
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extern __volatile int intr_mask;
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extern __volatile int softint_pending;
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extern int pxa2x0_imask[];
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void pxa2x0_do_pending(void);
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/*
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* Cotulla's integrated ICU doesn't have IRQ0..7, so
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* we map software interrupts to bit 0..3
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*/
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#define SI_TO_IRQBIT(si) (1U<<(si))
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static __inline void
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pxa2x0_setipl(int new)
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{
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current_spl_level = new;
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intr_mask = pxa2x0_imask[current_spl_level];
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write_icu( SAIPIC_MR, intr_mask );
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}
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static __inline void
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pxa2x0_splx(int new)
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{
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int psw;
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psw = disable_interrupts(I32_bit);
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pxa2x0_setipl(new);
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restore_interrupts(psw);
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/* If there are software interrupts to process, do it. */
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if (softint_pending & intr_mask)
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pxa2x0_do_pending();
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}
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static __inline int
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pxa2x0_splraise(int ipl)
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{
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int old, psw;
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old = current_spl_level;
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if( ipl > current_spl_level ){
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psw = disable_interrupts(I32_bit);
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pxa2x0_setipl(ipl);
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restore_interrupts(psw);
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}
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return (old);
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}
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static __inline int
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pxa2x0_spllower(int ipl)
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{
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int old = current_spl_level;
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int psw = disable_interrupts(I32_bit);
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pxa2x0_splx(ipl);
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restore_interrupts(psw);
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return(old);
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}
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static __inline void
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pxa2x0_setsoftintr(int si)
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{
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atomic_set_bit( (u_int *)&softint_pending, SI_TO_IRQBIT(si) );
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/* Process unmasked pending soft interrupts. */
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if ( softint_pending & intr_mask )
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pxa2x0_do_pending();
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}
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/*
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* An useful function for interrupt handlers.
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* XXX: This shouldn't be here.
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*/
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static __inline int
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find_first_bit( uint32_t bits )
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{
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int count;
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/* since CLZ is available only on ARMv5, this isn't portable
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* to all ARM CPUs. This file is for PXA2[15]0 processor.
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*/
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asm( "clz %0, %1" : "=r" (count) : "r" (bits) );
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return 31-count;
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}
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int _splraise(int);
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int _spllower(int);
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void splx(int);
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void _setsoftintr(int);
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#if !defined(EVBARM_SPL_NOINLINE)
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#define splx(new) pxa2x0_splx(new)
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#define _spllower(ipl) pxa2x0_spllower(ipl)
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#define _splraise(ipl) pxa2x0_splraise(ipl)
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#define _setsoftintr(si) pxa2x0_setsoftintr(si)
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#endif /* !EVBARM_SPL_NOINTR */
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/*
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* This function *MUST* be called very early on in a port's
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* initarm() function, before ANY spl*() functions are called.
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*
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* The parameter is the virtual address of the PXA2x0's Interrupt
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* Controller registers.
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*/
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void pxa2x0_intr_bootstrap(vaddr_t);
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void pxa2x0_irq_handler(void *);
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void *pxa2x0_intr_establish(int irqno, int level,
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int (*func)(void *), void *cookie);
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void pxa2x0_update_intr_masks(int irqno, int level);
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extern __volatile int current_spl_level;
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#endif /* ! _LOCORE */
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#endif /* _PXA2X0_INTR_H_ */
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