400 lines
10 KiB
C
400 lines
10 KiB
C
/* $NetBSD: becc_pci.c,v 1.6 2003/10/31 01:12:06 thorpej Exp $ */
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/*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI configuration support for the ADI Engineering Big Endian Companion
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* Chip.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: becc_pci.c,v 1.6 2003/10/31 01:12:06 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <arm/xscale/beccreg.h>
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#include <arm/xscale/beccvar.h>
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#include <dev/pci/ppbreg.h>
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#include <dev/pci/pciconf.h>
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#include "opt_pci.h"
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#include "pci.h"
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void becc_pci_attach_hook(struct device *, struct device *,
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struct pcibus_attach_args *);
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int becc_pci_bus_maxdevs(void *, int);
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pcitag_t becc_pci_make_tag(void *, int, int, int);
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void becc_pci_decompose_tag(void *, pcitag_t, int *, int *,
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int *);
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pcireg_t becc_pci_conf_read(void *, pcitag_t, int);
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void becc_pci_conf_write(void *, pcitag_t, int, pcireg_t);
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int becc_pci_intr_map(struct pci_attach_args *,
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pci_intr_handle_t *);
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const char *becc_pci_intr_string(void *, pci_intr_handle_t);
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const struct evcnt *becc_pci_intr_evcnt(void *, pci_intr_handle_t);
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void *becc_pci_intr_establish(void *, pci_intr_handle_t,
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int, int (*)(void *), void *);
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void becc_pci_intr_disestablish(void *, void *);
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#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
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#define PCI_CONF_UNLOCK(s) restore_interrupts((s))
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#if 0
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#define DPRINTF(x) printf(x)
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#else
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#define DPRINTF(x)
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#endif
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void
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becc_pci_init(pci_chipset_tag_t pc, void *cookie)
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{
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#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
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struct becc_softc *sc = cookie;
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struct extent *ioext, *memext;
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#endif
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pc->pc_conf_v = cookie;
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pc->pc_attach_hook = becc_pci_attach_hook;
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pc->pc_bus_maxdevs = becc_pci_bus_maxdevs;
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pc->pc_make_tag = becc_pci_make_tag;
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pc->pc_decompose_tag = becc_pci_decompose_tag;
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pc->pc_conf_read = becc_pci_conf_read;
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pc->pc_conf_write = becc_pci_conf_write;
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pc->pc_intr_v = cookie;
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pc->pc_intr_map = becc_pci_intr_map;
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pc->pc_intr_string = becc_pci_intr_string;
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pc->pc_intr_evcnt = becc_pci_intr_evcnt;
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pc->pc_intr_establish = becc_pci_intr_establish;
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pc->pc_intr_disestablish = becc_pci_intr_disestablish;
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#if NPCI > 0 && defined(PCI_NETBSD_CONFIGURE)
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/*
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* Configure the PCI bus.
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*
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* XXX We need to revisit this. We only configure the Secondary
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* bus (and its children). The bus configure code needs changes
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* to support how the busses are arranged on this chip. We also
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* need to only configure devices in the private device space on
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* the Secondary bus.
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*/
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/* Reserve the bottom 32K of the PCI address space. */
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ioext = extent_create("pciio", sc->sc_ioout_xlate + (32 * 1024),
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sc->sc_ioout_xlate + (64 * 1024) - 1,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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memext = extent_create("pcimem", sc->sc_owin_xlate[0],
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sc->sc_owin_xlate[0] + BECC_PCI_MEM1_SIZE - 1,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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aprint_normal("%s: configuring PCI bus\n", sc->sc_dev.dv_xname);
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pci_configure_bus(pc, ioext, memext, NULL, 0, arm_dcache_align);
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extent_destroy(ioext);
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extent_destroy(memext);
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#endif
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}
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void
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pci_conf_interrupt(pci_chipset_tag_t pc, int a, int b, int c, int d, int *p)
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{
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}
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void
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becc_pci_attach_hook(struct device *parent, struct device *self,
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struct pcibus_attach_args *pba)
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{
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/* Nothing to do. */
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}
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int
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becc_pci_bus_maxdevs(void *v, int busno)
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{
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return (32);
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}
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pcitag_t
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becc_pci_make_tag(void *v, int b, int d, int f)
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{
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return ((b << 16) | (d << 11) | (f << 8));
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}
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void
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becc_pci_decompose_tag(void *v, pcitag_t tag, int *bp, int *dp, int *fp)
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{
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if (bp != NULL)
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*bp = (tag >> 16) & 0xff;
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if (dp != NULL)
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*dp = (tag >> 11) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> 8) & 0x7;
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}
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struct pciconf_state {
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uint32_t ps_offset;
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int ps_b, ps_d, ps_f;
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int ps_type;
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};
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static int
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becc_pci_conf_setup(struct becc_softc *sc, pcitag_t tag, int offset,
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struct pciconf_state *ps)
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{
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becc_pci_decompose_tag(sc, tag, &ps->ps_b, &ps->ps_d, &ps->ps_f);
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/*
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* If the bus # is the same as our own, then use Type 0 cycles,
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* else use Type 1.
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*/
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if (ps->ps_b == 0) {
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/* XXX This is a platform-specific parameter. */
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if (ps->ps_d > (14 - BECC_IDSEL_BIT))
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return (1);
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ps->ps_offset = (1U << (ps->ps_d + BECC_IDSEL_BIT)) |
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(ps->ps_f << 8) | offset;
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ps->ps_type = 0;
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} else {
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/* The tag is already in the correct format. */
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ps->ps_offset = tag | offset | 1;
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ps->ps_type = 1;
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}
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return (0);
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}
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static int becc_pci_conf_cleanup(struct becc_softc *sc);
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static int
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becc_pci_conf_cleanup(struct becc_softc *sc)
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{
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uint32_t reg;
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int err=0;
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BECC_CSR_WRITE(BECC_POCR, 0);
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reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);
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if (reg & 0xf9000000) {
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DPRINTF((" ** pci status error: %08x (%08x) **\n",
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reg, reg & 0xf9000000));
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err = 1;
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becc_pcicore_write(sc, PCI_COMMAND_STATUS_REG,
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reg & 0xf900ffff);
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reg = becc_pcicore_read(sc, PCI_COMMAND_STATUS_REG);
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DPRINTF((" ** pci status after clearing: %08x (%08x) **\n",
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reg, reg & 0xf9000000));
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}
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reg = BECC_CSR_READ(BECC_PMISR);
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if (reg & 0x000f000d) {
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DPRINTF((" ** pci master isr: %08x (%08x) **\n",
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reg, reg & 0x000f000d));
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err = 1;
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BECC_CSR_WRITE(BECC_PMISR, reg & 0x000f000d);
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reg = BECC_CSR_READ(BECC_PMISR);
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DPRINTF((" ** pci master isr after clearing: %08x (%08x) **\n",
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reg, reg & 0x000f000d));
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}
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reg = BECC_CSR_READ(BECC_PSISR);
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if (reg & 0x000f0210) {
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DPRINTF((" ** pci slave isr: %08x (%08x) **\n",
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reg, reg & 0x000f0210));
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err = 1;
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BECC_CSR_WRITE(BECC_PSISR, reg & 0x000f0210);
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reg = BECC_CSR_READ(BECC_PSISR);
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DPRINTF((" ** pci slave isr after clearing: %08x (%08x) **\n",
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reg, reg & 0x000f0210));
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}
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return err;
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}
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pcireg_t
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becc_pci_conf_read(void *v, pcitag_t tag, int offset)
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{
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struct becc_softc *sc = v;
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struct pciconf_state ps;
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vaddr_t va;
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pcireg_t rv;
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u_int s;
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if (becc_pci_conf_setup(sc, tag, offset, &ps))
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return ((pcireg_t) -1);
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/*
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* Skip device 0 (the BECC itself). We don't want it
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* to appear as part of the PCI device space.
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*/
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if (ps.ps_b == 0 && ps.ps_d == 0)
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return ((pcireg_t) -1);
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PCI_CONF_LOCK(s);
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va = sc->sc_pci_cfg_base + ps.ps_offset;
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BECC_CSR_WRITE(BECC_POCR, ps.ps_type);
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if (badaddr_read((void *) va, sizeof(rv), &rv)) {
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/* XXX Check master/target abort? */
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#if 0
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printf("conf_read: %d/%d/%d bad address\n",
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ps.ps_b, ps.ps_d, ps.ps_f);
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#endif
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rv = (pcireg_t) -1;
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}
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if (becc_pci_conf_cleanup(sc))
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rv = (pcireg_t) -1;
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PCI_CONF_UNLOCK(s);
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return (rv);
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}
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void
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becc_pci_conf_write(void *v, pcitag_t tag, int offset, pcireg_t val)
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{
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struct becc_softc *sc = v;
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struct pciconf_state ps;
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vaddr_t va;
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u_int s;
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if (becc_pci_conf_setup(sc, tag, offset, &ps))
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return;
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PCI_CONF_LOCK(s);
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BECC_CSR_WRITE(BECC_POCR, ps.ps_type);
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va = sc->sc_pci_cfg_base + ps.ps_offset;
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*(__volatile pcireg_t *)va = val;
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becc_pci_conf_cleanup(sc);
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PCI_CONF_UNLOCK(s);
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}
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int
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becc_pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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int irq;
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if (pa->pa_bus == 0) {
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switch (pa->pa_device) {
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case 1: irq = ICU_PCI_INTB; break; /* Ethernet #0 */
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case 2: irq = ICU_PCI_INTC; break; /* Ethernet #1 */
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case 3: /* Card slot */
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switch (pa->pa_intrpin) {
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case 1: irq = ICU_PCI_INTA; break;
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case 2: irq = ICU_PCI_INTB; break;
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case 3: irq = ICU_PCI_INTC; break;
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case 4: irq = ICU_PCI_INTD; break;
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default:
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printf("becc_pci_intr_map: bogus pin: %d\n",
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pa->pa_intrpin);
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return (1);
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}
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break;
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default:
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printf("becc_pci_intr_map: bogus device: %d\n",
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pa->pa_device);
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return (1);
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}
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} else {
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switch (pa->pa_intrpin) {
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case 1: irq = ICU_PCI_INTA; break;
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case 2: irq = ICU_PCI_INTB; break;
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case 3: irq = ICU_PCI_INTC; break;
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case 4: irq = ICU_PCI_INTD; break;
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default:
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printf("becc_pci_intr_map: bogus pin: %d\n",
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pa->pa_intrpin);
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return (1);
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}
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}
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*ihp = irq;
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return (0);
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}
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const char *
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becc_pci_intr_string(void *v, pci_intr_handle_t ih)
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{
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return (becc_irqnames[ih]);
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}
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const struct evcnt *
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becc_pci_intr_evcnt(void *v, pci_intr_handle_t ih)
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{
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/* XXX For now. */
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return (NULL);
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}
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void *
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becc_pci_intr_establish(void *v, pci_intr_handle_t ih, int ipl,
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int (*func)(void *), void *arg)
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{
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return (becc_intr_establish(ih, ipl, func, arg));
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}
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void
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becc_pci_intr_disestablish(void *v, void *cookie)
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{
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becc_intr_disestablish(cookie);
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}
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