708 lines
16 KiB
C
708 lines
16 KiB
C
/* $NetBSD: dz.c,v 1.13 1998/11/05 19:48:05 ragge Exp $ */
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/*
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* Copyright (c) 1996 Ken C. Wellsch. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/ioctl.h>
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#include <sys/tty.h>
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#include <sys/proc.h>
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#include <sys/map.h>
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#include <sys/buf.h>
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#include <sys/conf.h>
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#include <sys/file.h>
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#include <sys/uio.h>
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#include <sys/kernel.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#ifdef DDB
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#include <dev/cons.h>
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#endif
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#include <machine/pte.h>
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#include <machine/trap.h>
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#include <machine/cpu.h>
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#include <vax/uba/ubareg.h>
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#include <vax/uba/ubavar.h>
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#include <vax/uba/dzreg.h>
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#include <vax/uba/dzvar.h>
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#include "ioconf.h"
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/* A DZ-11 has 8 ports while a DZV/DZQ-11 has only 4. We use 8 by default */
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#define NDZLINE 8
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#define DZ_C2I(c) ((c)<<3) /* convert controller # to index */
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#define DZ_I2C(c) ((c)>>3) /* convert minor to controller # */
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#define DZ_PORT(u) ((u)&07) /* extract the port # */
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/* Flags used to monitor modem bits, make them understood outside driver */
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#define DML_DTR TIOCM_DTR
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#define DML_DCD TIOCM_CD
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#define DML_RI TIOCM_RI
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#define DML_BRK 0100000 /* no equivalent, we will mask */
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static struct speedtab dzspeedtab[] =
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{
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{ 0, 0 },
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{ 50, DZ_LPR_B50 },
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{ 75, DZ_LPR_B75 },
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{ 110, DZ_LPR_B110 },
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{ 134, DZ_LPR_B134 },
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{ 150, DZ_LPR_B150 },
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{ 300, DZ_LPR_B300 },
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{ 600, DZ_LPR_B600 },
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{ 1200, DZ_LPR_B1200 },
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{ 1800, DZ_LPR_B1800 },
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{ 2000, DZ_LPR_B2000 },
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{ 2400, DZ_LPR_B2400 },
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{ 3600, DZ_LPR_B3600 },
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{ 4800, DZ_LPR_B4800 },
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{ 7200, DZ_LPR_B7200 },
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{ 9600, DZ_LPR_B9600 },
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{ 19200, DZ_LPR_B19200 },
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{ -1, -1 }
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};
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static void dzstart __P((struct tty *));
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static int dzparam __P((struct tty *, struct termios *));
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static unsigned dzmctl __P((struct dz_softc *, int, int, int));
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static void dzscan __P((void *));
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cdev_decl(dz);
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/*
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* The DZ series doesn't interrupt on carrier transitions,
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* so we have to use a timer to watch it.
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*/
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int dz_timer = 0; /* true if timer started */
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#define DZ_DZ 8 /* Unibus DZ-11 board linecount */
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#define DZ_DZV 4 /* Q-bus DZV-11 or DZQ-11 */
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void
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dzattach(sc)
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struct dz_softc *sc;
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{
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register int n;
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sc->sc_rxint = sc->sc_brk = 0;
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sc->sc_dr.dr_tcrw = (void *)sc->sc_dr.dr_tcr;
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*sc->sc_dr.dr_csr = (DZ_CSR_MSE | DZ_CSR_RXIE | DZ_CSR_TXIE);
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*sc->sc_dr.dr_dtr = 0; /* Make sure DTR bits are zero */
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*sc->sc_dr.dr_break = 0; /* Status of BREAK bits, all off */
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/* Initialize our softc structure. Should be done in open? */
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for (n = 0; n < sc->sc_type; n++)
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sc->sc_dz[n].dz_tty = ttymalloc();
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/* Alas no interrupt on modem bit changes, so we manually scan */
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if (dz_timer == 0) {
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dz_timer = 1;
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timeout(dzscan, (void *)0, hz);
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}
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printf("\n");
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return;
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}
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/* Receiver Interrupt */
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void
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dzrint(cntlr)
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int cntlr;
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{
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struct dz_softc *sc = dz_cd.cd_devs[cntlr];
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register struct tty *tp;
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register int cc, line;
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register unsigned c;
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int overrun = 0;
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sc->sc_rxint++;
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while ((c = *sc->sc_dr.dr_rbuf) & DZ_RBUF_DATA_VALID) {
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cc = c & 0xFF;
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line = DZ_PORT(c>>8);
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tp = sc->sc_dz[line].dz_tty;
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/* Must be caught early */
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if (sc->sc_catch && (*sc->sc_catch)(line, cc))
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continue;
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if (!(tp->t_state & TS_ISOPEN)) {
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wakeup((caddr_t)&tp->t_rawq);
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continue;
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}
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if ((c & DZ_RBUF_OVERRUN_ERR) && overrun == 0) {
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log(LOG_WARNING, "%s: silo overflow, line %d\n",
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sc->sc_dev.dv_xname, line);
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overrun = 1;
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}
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/* A BREAK key will appear as a NULL with a framing error */
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if (c & DZ_RBUF_FRAMING_ERR)
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cc |= TTY_FE;
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if (c & DZ_RBUF_PARITY_ERR)
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cc |= TTY_PE;
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#if defined(DDB) && (defined(VAX410) || defined(VAX43) || defined(VAX46))
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if (tp->t_dev == cn_tab->cn_dev) {
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int j = kdbrint(cc);
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if (j == 1) /* Escape received, just return */
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continue;
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if (j == 2) /* Second char wasn't 'D' */
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(*linesw[tp->t_line].l_rint)(27, tp);
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}
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#endif
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(*linesw[tp->t_line].l_rint)(cc, tp);
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}
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}
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/* Transmitter Interrupt */
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void
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dzxint(cntlr)
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int cntlr;
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{
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register struct dz_softc *sc = dz_cd.cd_devs[cntlr];
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register struct tty *tp;
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register struct clist *cl;
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register int line, ch, csr;
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u_char tcr;
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/*
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* Switch to POLLED mode.
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* Some simple measurements indicated that even on
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* one port, by freeing the scanner in the controller
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* by either providing a character or turning off
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* the port when output is complete, the transmitter
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* was ready to accept more output when polled again.
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* With just two ports running the game "worms,"
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* almost every interrupt serviced both transmitters!
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* Each UART is double buffered, so if the scanner
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* is quick enough and timing works out, we can even
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* feed the same port twice.
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*
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* Ragge 980517:
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* Do not need to turn off interrupts, already at interrupt level.
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* Remove the pdma stuff; no great need of it right now.
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*/
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while (((csr = *sc->sc_dr.dr_csr) & DZ_CSR_TX_READY) != 0) {
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line = DZ_PORT(csr>>8);
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tp = sc->sc_dz[line].dz_tty;
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cl = &tp->t_outq;
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tp->t_state &= ~TS_BUSY;
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/* Just send out a char if we have one */
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/* As long as we can fill the chip buffer, we just loop here */
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if (cl->c_cc) {
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tp->t_state |= TS_BUSY;
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ch = getc(cl);
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*sc->sc_dr.dr_tbuf = ch;
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continue;
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}
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/* Nothing to send; clear the scan bit */
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/* Clear xmit scanner bit; dzstart may set it again */
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tcr = *sc->sc_dr.dr_tcrw & 255;
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tcr &= ~(1 << line);
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*sc->sc_dr.dr_tcr = tcr;
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if (tp->t_state & TS_FLUSH)
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tp->t_state &= ~TS_FLUSH;
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else
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ndflush (&tp->t_outq, cl->c_cc);
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if (tp->t_line)
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(*linesw[tp->t_line].l_start)(tp);
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else
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dzstart(tp);
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}
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}
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int
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dzopen(dev, flag, mode, p)
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dev_t dev;
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int flag, mode;
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struct proc *p;
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{
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register struct tty *tp;
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register int unit, line;
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struct dz_softc *sc;
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int s, error = 0;
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unit = DZ_I2C(minor(dev));
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line = DZ_PORT(minor(dev));
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if (unit >= dz_cd.cd_ndevs || dz_cd.cd_devs[unit] == NULL)
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return (ENXIO);
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sc = dz_cd.cd_devs[unit];
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if (line >= sc->sc_type)
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return ENXIO;
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tp = sc->sc_dz[line].dz_tty;
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if (tp == NULL)
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return (ENODEV);
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tp->t_oproc = dzstart;
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tp->t_param = dzparam;
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tp->t_dev = dev;
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if ((tp->t_state & TS_ISOPEN) == 0) {
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ttychars(tp);
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if (tp->t_ispeed == 0) {
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tp->t_iflag = TTYDEF_IFLAG;
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tp->t_oflag = TTYDEF_OFLAG;
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tp->t_cflag = TTYDEF_CFLAG;
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tp->t_lflag = TTYDEF_LFLAG;
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tp->t_ispeed = tp->t_ospeed = TTYDEF_SPEED;
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}
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(void) dzparam(tp, &tp->t_termios);
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ttsetwater(tp);
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} else if ((tp->t_state & TS_XCLUDE) && p->p_ucred->cr_uid != 0)
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return (EBUSY);
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/* Use DMBIS and *not* DMSET or else we clobber incoming bits */
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if (dzmctl(sc, line, DML_DTR, DMBIS) & DML_DCD)
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tp->t_state |= TS_CARR_ON;
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s = spltty();
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while (!(flag & O_NONBLOCK) && !(tp->t_cflag & CLOCAL) &&
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!(tp->t_state & TS_CARR_ON)) {
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tp->t_wopen++;
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error = ttysleep(tp, (caddr_t)&tp->t_rawq,
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TTIPRI | PCATCH, ttopen, 0);
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tp->t_wopen--;
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if (error)
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break;
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}
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(void) splx(s);
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if (error)
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return (error);
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if (sc->sc_rxon)
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(*sc->sc_rxon)();
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if (sc->sc_txon)
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(*sc->sc_txon)();
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return ((*linesw[tp->t_line].l_open)(dev, tp));
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}
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/*ARGSUSED*/
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int
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dzclose(dev, flag, mode, p)
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dev_t dev;
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int flag, mode;
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struct proc *p;
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{
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struct dz_softc *sc;
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register struct tty *tp;
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register int unit, line;
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unit = DZ_I2C(minor(dev));
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line = DZ_PORT(minor(dev));
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sc = dz_cd.cd_devs[unit];
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tp = sc->sc_dz[line].dz_tty;
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(*linesw[tp->t_line].l_close)(tp, flag);
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/* Make sure a BREAK state is not left enabled. */
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(void) dzmctl(sc, line, DML_BRK, DMBIC);
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/* Do a hangup if so required. */
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if ((tp->t_cflag & HUPCL) || tp->t_wopen || !(tp->t_state & TS_ISOPEN))
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(void) dzmctl(sc, line, 0, DMSET);
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return (ttyclose(tp));
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}
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int
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dzread (dev, uio, flag)
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dev_t dev;
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struct uio *uio;
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{
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register struct tty *tp;
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struct dz_softc *sc;
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sc = dz_cd.cd_devs[DZ_I2C(minor(dev))];
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tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty;
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return ((*linesw[tp->t_line].l_read)(tp, uio, flag));
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}
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int
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dzwrite (dev, uio, flag)
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dev_t dev;
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struct uio *uio;
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{
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register struct tty *tp;
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struct dz_softc *sc;
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sc = dz_cd.cd_devs[DZ_I2C(minor(dev))];
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tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty;
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return ((*linesw[tp->t_line].l_write)(tp, uio, flag));
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}
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/*ARGSUSED*/
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int
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dzioctl (dev, cmd, data, flag, p)
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dev_t dev;
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u_long cmd;
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caddr_t data;
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int flag;
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struct proc *p;
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{
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struct dz_softc *sc;
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register struct tty *tp;
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register int unit, line;
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int error;
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unit = DZ_I2C(minor(dev));
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line = DZ_PORT(minor(dev));
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sc = dz_cd.cd_devs[unit];
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tp = sc->sc_dz[line].dz_tty;
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error = (*linesw[tp->t_line].l_ioctl)(tp, cmd, data, flag, p);
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if (error >= 0)
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return (error);
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error = ttioctl(tp, cmd, data, flag, p);
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if (error >= 0)
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return (error);
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switch (cmd) {
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case TIOCSBRK:
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(void) dzmctl(sc, line, DML_BRK, DMBIS);
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break;
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case TIOCCBRK:
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(void) dzmctl(sc, line, DML_BRK, DMBIC);
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break;
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case TIOCSDTR:
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(void) dzmctl(sc, line, DML_DTR, DMBIS);
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break;
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case TIOCCDTR:
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(void) dzmctl(sc, line, DML_DTR, DMBIC);
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break;
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case TIOCMSET:
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(void) dzmctl(sc, line, *(int *)data, DMSET);
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break;
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case TIOCMBIS:
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(void) dzmctl(sc, line, *(int *)data, DMBIS);
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break;
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case TIOCMBIC:
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(void) dzmctl(sc, line, *(int *)data, DMBIC);
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break;
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case TIOCMGET:
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*(int *)data = (dzmctl(sc, line, 0, DMGET) & ~DML_BRK);
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break;
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default:
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return (ENOTTY);
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}
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return (0);
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}
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struct tty *
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dztty (dev)
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dev_t dev;
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{
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struct dz_softc *sc = dz_cd.cd_devs[DZ_I2C(minor(dev))];
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struct tty *tp = sc->sc_dz[DZ_PORT(minor(dev))].dz_tty;
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return (tp);
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}
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/*ARGSUSED*/
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void
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dzstop(tp, flag)
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register struct tty *tp;
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{
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if (tp->t_state & TS_BUSY)
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if (!(tp->t_state & TS_TTSTOP))
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tp->t_state |= TS_FLUSH;
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}
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void
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dzstart(tp)
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register struct tty *tp;
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{
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register struct dz_softc *sc;
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register struct clist *cl;
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register int unit, line, s;
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char state;
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unit = DZ_I2C(minor(tp->t_dev));
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line = DZ_PORT(minor(tp->t_dev));
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sc = dz_cd.cd_devs[unit];
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s = spltty();
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if (tp->t_state & (TS_TIMEOUT|TS_BUSY|TS_TTSTOP))
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return;
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cl = &tp->t_outq;
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if (cl->c_cc <= tp->t_lowat) {
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if (tp->t_state & TS_ASLEEP) {
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tp->t_state &= ~TS_ASLEEP;
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wakeup((caddr_t)cl);
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}
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selwakeup(&tp->t_wsel);
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}
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if (cl->c_cc == 0)
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return;
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tp->t_state |= TS_BUSY;
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state = (*sc->sc_dr.dr_tcrw) & 255;
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if ((state & (1 << line)) == 0) {
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*sc->sc_dr.dr_tcr = state | (1 << line);
|
|
}
|
|
dzxint(sc->sc_dev.dv_unit);
|
|
splx(s);
|
|
}
|
|
|
|
static int
|
|
dzparam(tp, t)
|
|
register struct tty *tp;
|
|
register struct termios *t;
|
|
{
|
|
struct dz_softc *sc;
|
|
register int cflag = t->c_cflag;
|
|
int unit, line;
|
|
int ispeed = ttspeedtab(t->c_ispeed, dzspeedtab);
|
|
int ospeed = ttspeedtab(t->c_ospeed, dzspeedtab);
|
|
register unsigned lpr;
|
|
int s;
|
|
|
|
unit = DZ_I2C(minor(tp->t_dev));
|
|
line = DZ_PORT(minor(tp->t_dev));
|
|
sc = dz_cd.cd_devs[unit];
|
|
|
|
/* check requested parameters */
|
|
if (ospeed < 0 || ispeed < 0 || ispeed != ospeed)
|
|
return (EINVAL);
|
|
|
|
tp->t_ispeed = t->c_ispeed;
|
|
tp->t_ospeed = t->c_ospeed;
|
|
tp->t_cflag = cflag;
|
|
|
|
if (ospeed == 0) {
|
|
(void) dzmctl(sc, line, 0, DMSET); /* hang up line */
|
|
return (0);
|
|
}
|
|
|
|
s = spltty();
|
|
|
|
lpr = DZ_LPR_RX_ENABLE | ((ispeed&0xF)<<8) | line;
|
|
|
|
switch (cflag & CSIZE)
|
|
{
|
|
case CS5:
|
|
lpr |= DZ_LPR_5_BIT_CHAR;
|
|
break;
|
|
case CS6:
|
|
lpr |= DZ_LPR_6_BIT_CHAR;
|
|
break;
|
|
case CS7:
|
|
lpr |= DZ_LPR_7_BIT_CHAR;
|
|
break;
|
|
default:
|
|
lpr |= DZ_LPR_8_BIT_CHAR;
|
|
break;
|
|
}
|
|
if (cflag & PARENB)
|
|
lpr |= DZ_LPR_PARENB;
|
|
if (cflag & PARODD)
|
|
lpr |= DZ_LPR_OPAR;
|
|
if (cflag & CSTOPB)
|
|
lpr |= DZ_LPR_2_STOP;
|
|
|
|
*sc->sc_dr.dr_lpr = lpr;
|
|
|
|
(void) splx(s);
|
|
return (0);
|
|
}
|
|
|
|
static unsigned
|
|
dzmctl(sc, line, bits, how)
|
|
register struct dz_softc *sc;
|
|
int line, bits, how;
|
|
{
|
|
register unsigned status;
|
|
register unsigned mbits;
|
|
register unsigned bit;
|
|
int s;
|
|
|
|
s = spltty();
|
|
|
|
mbits = 0;
|
|
|
|
bit = (1 << line);
|
|
|
|
/* external signals as seen from the port */
|
|
|
|
status = (*sc->sc_dr.dr_dcd | sc->sc_dsr);
|
|
|
|
if (status & bit)
|
|
mbits |= DML_DCD;
|
|
|
|
status = *sc->sc_dr.dr_ring;
|
|
|
|
if (status & bit)
|
|
mbits |= DML_RI;
|
|
|
|
/* internal signals/state delivered to port */
|
|
|
|
status = *sc->sc_dr.dr_dtr;
|
|
|
|
if (status & bit)
|
|
mbits |= DML_DTR;
|
|
|
|
if (sc->sc_brk & bit)
|
|
mbits |= DML_BRK;
|
|
|
|
switch (how)
|
|
{
|
|
case DMSET:
|
|
mbits = bits;
|
|
break;
|
|
|
|
case DMBIS:
|
|
mbits |= bits;
|
|
break;
|
|
|
|
case DMBIC:
|
|
mbits &= ~bits;
|
|
break;
|
|
|
|
case DMGET:
|
|
(void) splx(s);
|
|
return (mbits);
|
|
}
|
|
|
|
if (mbits & DML_DTR)
|
|
*sc->sc_dr.dr_dtr |= bit;
|
|
else
|
|
*sc->sc_dr.dr_dtr &= ~bit;
|
|
|
|
if (mbits & DML_BRK)
|
|
*sc->sc_dr.dr_break = (sc->sc_brk |= bit);
|
|
else
|
|
*sc->sc_dr.dr_break = (sc->sc_brk &= ~bit);
|
|
|
|
(void) splx(s);
|
|
return (mbits);
|
|
}
|
|
|
|
/*
|
|
* This is called by timeout() periodically.
|
|
* Check to see if modem status bits have changed.
|
|
*/
|
|
static void
|
|
dzscan(arg)
|
|
void *arg;
|
|
{
|
|
register struct dz_softc *sc;
|
|
register struct tty *tp;
|
|
register int n, bit, port;
|
|
unsigned csr;
|
|
int s;
|
|
|
|
s = spltty();
|
|
|
|
for (n = 0; n < dz_cd.cd_ndevs; n++) {
|
|
|
|
if (dz_cd.cd_devs[n] == NULL)
|
|
continue;
|
|
|
|
sc = dz_cd.cd_devs[n];
|
|
|
|
for (port = 0; port < sc->sc_type; port++) {
|
|
|
|
tp = sc->sc_dz[port].dz_tty;
|
|
bit = (1 << port);
|
|
|
|
if ((*sc->sc_dr.dr_dcd | sc->sc_dsr) & bit) {
|
|
if (!(tp->t_state & TS_CARR_ON))
|
|
(*linesw[tp->t_line].l_modem) (tp, 1);
|
|
} else if ((tp->t_state & TS_CARR_ON) &&
|
|
(*linesw[tp->t_line].l_modem)(tp, 0) == 0)
|
|
*sc->sc_dr.dr_tcr =
|
|
((*sc->sc_dr.dr_tcrw)&255) & ~bit;
|
|
}
|
|
|
|
/*
|
|
* If the RX interrupt rate is this high, switch
|
|
* the controller to Silo Alarm - which means don't
|
|
* interrupt until the RX silo has 16 characters in
|
|
* it (the silo is 64 characters in all).
|
|
* Avoid oscillating SA on and off by not turning
|
|
* if off unless the rate is appropriately low.
|
|
*/
|
|
|
|
csr = *sc->sc_dr.dr_csr;
|
|
|
|
if (sc->sc_rxint > (16*10)) {
|
|
if ((csr & DZ_CSR_SAE) == 0)
|
|
*sc->sc_dr.dr_csr = (csr | DZ_CSR_SAE);
|
|
} else if ((csr & DZ_CSR_SAE) != 0)
|
|
if (sc->sc_rxint < 10)
|
|
*sc->sc_dr.dr_csr = (csr & ~(DZ_CSR_SAE));
|
|
|
|
sc->sc_rxint = 0;
|
|
}
|
|
(void) splx(s);
|
|
timeout(dzscan, (void *)0, hz);
|
|
return;
|
|
}
|