130 lines
4.7 KiB
C
130 lines
4.7 KiB
C
/* $NetBSD: trap.h,v 1.11 2005/12/11 12:19:00 christos Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _SH5_TRAP_H
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#define _SH5_TRAP_H
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/*
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* SH5 Traps are identified by a value in the EXPEVT control register.
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*
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* We fabricate an AST trap: T_AST.
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*/
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/* Power-On Reset Exception (0x0) */
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#define T_POWERON 0x000 /* Power-On reset */
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/* General Exceptions (VBR + 0x100) */
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#define T_READPROT 0x0a0 /* Data Protection violation Read */
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#define T_WRITEPROT 0x0c0 /* Data Protection violation Write */
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#define T_RADDERR 0x0e0 /* Data Address error Read */
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#define T_WADDERR 0x100 /* Data Address error Write */
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#define T_FPUEXC 0x120 /* FPU exception */
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#define T_TRAP 0x160 /* Unconditional trap (syscall) */
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#define T_RESINST 0x180 /* Reserved instruction */
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#define T_ILLSLOT 0x1a0 /* Illegal slot exception */
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#define T_FPUDIS 0x800 /* FPU disabled */
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#define T_SLOTFPUDIS 0x820 /* Delay Slot FPU disabled */
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#define T_EXECPROT 0xaa0 /* Instruction Protection Violation */
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#define T_IADDERR 0xae0 /* Instruction Address Error */
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/* Debug Exceptions (RESVEC/DBRVEC + 0x100) */
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#define T_PANIC ?????
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#define T_CPURESET 0x020 /* CPU reset */
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#define T_DEBUGIA 0x900 /* Instruction Address Debug */
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#define T_DEBUGIV 0x920 /* Instruction Value Debug */
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#define T_BREAK 0x940 /* Software break */
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#define T_DEBUGOA 0x960 /* Operand Address Debug */
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#define T_DEBUGSS 0x980 /* Single Step Debug */
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/* Debug Interrupts (RESVEC/DBRVEC + 0x200) */
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/* Nothing */
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/* TLB Miss Exceptions (VBR + 0x400) */
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#define T_RTLBMISS 0x040 /* Data TLB miss read */
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#define T_WTLBMISS 0x060 /* Data TLB miss write */
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#define T_ITLBMISS 0xa40 /* Instruction TLB Miss Error */
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/* External Interrupts (VBR + 0x600) */
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/* Nothing */
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/* Software Exception Types */
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#define T_AST 0x0002 /* Asynchronous System Trap */
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#define T_NMI 0x0004 /* NMI trap */
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#define T_DIVZERO 0x0006 /* Integer divide by zero trap */
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/* Bit 0 set == trap came from user mode */
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#define T_USER 0x0001
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/*
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* TRAPA codes
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*/
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#define TRAPA_DIVZERO 0x00 /* Simulated Divide by zero trap */
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#define TRAPA_SYSCALL 0x80 /* NetBSD/sh5 native system call */
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/*
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* Critical section owners
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*/
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#define CRIT_FREE 0 /* Nobody is in the critical section */
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#define CRIT_EXIT 0x01 /* Flag bit for exiting crit section */
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#define CRIT_SYNC_EXCEPTION 0x02 /* Synchronous Exception Handler */
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#define CRIT_ASYNC_EXCEPTION 0x04 /* Asynchronous Exception Handler */
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#define CRIT_TLBMISS_TRAP 0x06 /* TLB Miss promoted to TRAP */
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#if defined(_KERNEL) && !defined(_LOCORE)
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extern void userret(struct lwp *);
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extern void trap(struct lwp *, struct trapframe *);
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extern void trapa(struct lwp *, struct trapframe *);
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extern void panic_trap(struct trapframe *, register_t, register_t,
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register_t);
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extern const char *trap_type(int);
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#if defined(DIAGNOSTIC) || defined(DDB)
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extern void dump_trapframe(void (*)(const char *, ...), const char *,
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struct trapframe *);
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#endif
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extern label_t *onfault;
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#endif
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#endif /* _SH5_TRAP_H */
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