4d3ab04c3b
consideration and avoid future code duplication. Ports wanting to enable detachment of controllers with compatibility-mapped channels will need to supply a pciide_machdep_compat_intr_disestablish() function.
255 lines
8.3 KiB
C
255 lines
8.3 KiB
C
/* $NetBSD: pciidevar.h,v 1.42 2010/11/06 00:29:09 jakllsch Exp $ */
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/*
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* Copyright (c) 1998 Christopher G. Demetriou. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_PCIIDEVAR_H_
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#define _DEV_PCI_PCIIDEVAR_H_
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/*
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* PCI IDE driver exported software structures.
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*
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* Author: Christopher G. Demetriou, March 2, 1998.
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*/
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#include <dev/ata/atavar.h>
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#include <dev/ic/wdcreg.h>
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#include <dev/ic/wdcvar.h>
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#include <sys/device_if.h>
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#include "opt_pciide.h"
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/* options passed via the 'flags' config keyword */
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#define PCIIDE_OPTIONS_DMA 0x01
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#define PCIIDE_OPTIONS_NODMA 0x02
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#ifndef ATADEBUG
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#define ATADEBUG
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#endif
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#define DEBUG_DMA 0x01
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#define DEBUG_XFERS 0x02
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#define DEBUG_FUNCS 0x08
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#define DEBUG_PROBE 0x10
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#ifdef ATADEBUG
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extern int atadebug_pciide_mask;
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#define ATADEBUG_PRINT(args, level) \
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if (atadebug_pciide_mask & (level)) printf args
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#else
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#define ATADEBUG_PRINT(args, level)
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#endif
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/*
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* While standard PCI IDE controllers only have 2 channels, it is
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* common for PCI SATA controllers to have more. Here we define
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* the maximum number of channels that any one PCI IDE device can
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* have.
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*/
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#define PCIIDE_MAX_CHANNELS 4
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struct pciide_softc {
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struct wdc_softc sc_wdcdev; /* common wdc definitions */
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pci_chipset_tag_t sc_pc; /* PCI registers info */
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pcitag_t sc_tag;
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void *sc_pci_ih; /* PCI interrupt handle */
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#if NATA_DMA
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int sc_dma_ok; /* bus-master DMA info */
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/*
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* sc_dma_ioh may only be used to allocate the dma_iohs
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* array in the channels (see below), or by chip-dependent
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* code that knows what it's doing, as the registers may
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* be laid out differently. All code in pciide_common.c
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* must use the channel->dma_iohs array.
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*/
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bus_space_tag_t sc_dma_iot;
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bus_space_handle_t sc_dma_ioh;
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bus_size_t sc_dma_ios;
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bus_dma_tag_t sc_dmat;
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/*
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* Some controllers might have DMA restrictions other than
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* the norm.
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*/
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bus_size_t sc_dma_maxsegsz;
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bus_size_t sc_dma_boundary;
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/* For VIA/AMD/nVidia */
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bus_addr_t sc_apo_regbase;
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/* For Cypress */
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const struct cy82c693_handle *sc_cy_handle;
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int sc_cy_compatchan;
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/* for SiS */
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u_int8_t sis_type;
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/*
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* For Silicon Image SATALink, Serverworks SATA, Artisea SATA
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* and Promise SATA
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*/
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bus_space_tag_t sc_ba5_st;
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bus_space_handle_t sc_ba5_sh;
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bus_size_t sc_ba5_ss;
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int sc_ba5_en;
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#endif /* NATA_DMA */
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/* Vendor info (for interpreting Chip description) */
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pcireg_t sc_pci_id;
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/* Chip description */
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const struct pciide_product_desc *sc_pp;
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/* common definitions */
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struct ata_channel *wdc_chanarray[PCIIDE_MAX_CHANNELS];
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/* internal bookkeeping */
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struct pciide_channel { /* per-channel data */
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struct ata_channel ata_channel; /* generic part */
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const char *name;
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int compat; /* is it compat? */
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void *ih; /* compat or pci handle */
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bus_space_handle_t ctl_baseioh; /* ctrl regs blk, native mode */
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bus_size_t ctl_ios;
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#if NATA_DMA
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/* DMA tables and DMA map for xfer, for each drive */
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struct pciide_dma_maps {
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bus_dma_segment_t dmamap_table_seg;
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int dmamap_table_nseg;
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bus_dmamap_t dmamap_table;
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struct idedma_table *dma_table;
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bus_dmamap_t dmamap_xfer;
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int dma_flags;
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} dma_maps[ATA_MAXDRIVES];
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bus_space_handle_t dma_iohs[IDEDMA_NREGS];
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/*
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* Some controllers require certain bits to
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* always be set for proper operation of the
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* controller. Set those bits here, if they're
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* required.
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*/
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uint8_t idedma_cmd;
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#endif /* NATA_DMA */
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} pciide_channels[PCIIDE_MAX_CHANNELS];
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pcireg_t sc_pm_reg[4];
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};
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/* Given an ata_channel, get the pciide_softc. */
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#define CHAN_TO_PCIIDE(chp) ((struct pciide_softc *) (chp)->ch_atac)
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/* Given an ata_channel, get the pciide_channel. */
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#define CHAN_TO_PCHAN(chp) ((struct pciide_channel *) (chp))
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struct pciide_product_desc {
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u_int32_t ide_product;
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int ide_flags;
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const char *ide_name;
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/* map and setup chip, probe drives */
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void (*chip_map)(struct pciide_softc*, struct pci_attach_args*);
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};
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/* Flags for ide_flags */
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#define IDE_16BIT_IOSPACE 0x0002 /* I/O space BARS ignore upper word */
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/* inlines for reading/writing 8-bit PCI registers */
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static inline u_int8_t pciide_pci_read(pci_chipset_tag_t, pcitag_t, int);
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static inline void pciide_pci_write(pci_chipset_tag_t, pcitag_t,
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int, u_int8_t);
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static inline u_int8_t
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pciide_pci_read(pci_chipset_tag_t pc, pcitag_t pa, int reg)
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{
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return (pci_conf_read(pc, pa, (reg & ~0x03)) >>
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((reg & 0x03) * 8) & 0xff);
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}
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static inline void
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pciide_pci_write(pci_chipset_tag_t pc, pcitag_t pa, int reg, uint8_t val)
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{
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pcireg_t pcival;
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pcival = pci_conf_read(pc, pa, (reg & ~0x03));
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pcival &= ~(0xff << ((reg & 0x03) * 8));
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pcival |= (val << ((reg & 0x03) * 8));
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pci_conf_write(pc, pa, (reg & ~0x03), pcival);
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}
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void default_chip_map(struct pciide_softc*, struct pci_attach_args*);
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void sata_setup_channel(struct ata_channel*);
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void pciide_channel_dma_setup(struct pciide_channel *);
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int pciide_dma_table_setup(struct pciide_softc*, int, int);
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void pciide_dma_table_teardown(struct pciide_softc *, int, int);
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int pciide_dma_dmamap_setup(struct pciide_softc *, int, int,
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void *, size_t, int);
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int pciide_dma_init(void*, int, int, void *, size_t, int);
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void pciide_dma_start(void*, int, int);
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int pciide_dma_finish(void*, int, int, int);
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void pciide_irqack(struct ata_channel *);
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/*
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* Functions defined by machine-dependent code.
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*/
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/* Attach compat interrupt handler, returning handle or NULL if failed. */
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#ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
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void *pciide_machdep_compat_intr_establish(device_t,
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struct pci_attach_args *, int, int (*)(void *), void *);
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#endif
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#ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH
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void pciide_machdep_compat_intr_disestablish(device_t,
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pci_chipset_tag_t, int, void *);
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#endif
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const struct pciide_product_desc* pciide_lookup_product
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(u_int32_t, const struct pciide_product_desc *);
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void pciide_common_attach(struct pciide_softc *, struct pci_attach_args *,
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const struct pciide_product_desc *);
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int pciide_common_detach(struct pciide_softc *, int);
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int pciide_detach(device_t, int);
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int pciide_chipen(struct pciide_softc *, struct pci_attach_args *);
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void pciide_mapregs_compat(struct pci_attach_args *,
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struct pciide_channel *, int);
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void pciide_mapregs_native(struct pci_attach_args *,
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struct pciide_channel *, int (*pci_intr)(void *));
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void pciide_mapreg_dma(struct pciide_softc *,
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struct pci_attach_args *);
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int pciide_chansetup(struct pciide_softc *, int, pcireg_t);
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void pciide_mapchan(struct pci_attach_args *,
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struct pciide_channel *, pcireg_t, int (*pci_intr)(void *));
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void pciide_map_compat_intr(struct pci_attach_args *,
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struct pciide_channel *, int);
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void pciide_unmap_compat_intr(pci_chipset_tag_t,
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struct pciide_channel *, int);
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int pciide_compat_intr(void *);
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int pciide_pci_intr(void *);
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#endif /* _DEV_PCI_PCIIDEVAR_H_ */
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