154 lines
5.8 KiB
C
154 lines
5.8 KiB
C
/* $NetBSD: if_bcereg.h,v 1.4 2005/12/11 12:22:49 christos Exp $ */
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/*
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* Copyright (c) 2003 Clifford Wright. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* Broadcom BCM440x */
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/* PCI registers defined in the PCI 2.2 spec. */
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#define BCE_PCI_BAR0 0x10
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/* Sonics SB register access */
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#define BCE_REG_WIN 0x80
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#define BCE_SONICS_WIN 0x18002000
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/* Sonics PCI control */
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#define BCE_SPCI_TR2 0x0108 /* Sonics to PCI translation
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* 2 */
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/* bit defines */
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#define SBTOPCI_PREF 0x4 /* prefetch enable */
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#define SBTOPCI_BURST 0x8 /* burst enable */
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#define BCE_SBINTVEC 0x0f94
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/* interrupt bits */
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#define SBIV_ENET0 0x02 /* enable for enet 0 */
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#define SBIV_ENET1 0x40 /* enable for enet 1 */
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/* Host Interface Registers */
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#define BCE_DEVCTL 0x0000 /* device control */
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/* device control bits */
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#define BCE_DC_IP 0x00000400 /* internal phy present */
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#define BCE_DC_ER 0x00008000 /* ephy reset */
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/* Interrupt Control */
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#define BCE_INT_STS 0x0020
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#define BCE_INT_MASK 0x0024
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/* bits for both status, and mask */
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#define I_TO 0x00000080 /* general timeout */
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#define I_PC 0x00000400 /* descriptor error */
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#define I_PD 0x00000800 /* data error */
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#define I_DE 0x00001000 /* desc. protocol error */
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#define I_RU 0x00002000 /* rx desc. underflow */
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#define I_RO 0x00004000 /* rx fifo overflow */
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#define I_XU 0x00008000 /* tx fifo underflow */
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#define I_RI 0x00010000 /* receive interrupt */
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#define I_XI 0x01000000 /* transmit interrupt */
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/* Ethernet MAC Control */
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#define BCE_MACCTL 0x00A8 /* ethernet mac control */
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/* mac control bits */
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#define BCE_EMC_CG 0x00000001 /* crc32 generation */
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/* DMA Interrupt control */
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#define BCE_DMAI_CTL 0x0100
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/* DMA registers */
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#define BCE_DMA_TXCTL 0x0200 /* transmit control */
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/* transmit control bits */
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#define XC_XE 0x1 /* transmit enable */
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#define XC_LE 0x4 /* loopback enable */
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#define BCE_DMA_TXADDR 0x0204 /* tx ring base address */
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#define BCE_DMA_DPTR 0x0208 /* last tx descriptor */
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#define BCE_DMA_TXSTATUS 0x020C /* active desc, etc */
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#define BCE_DMA_RXCTL 0x0210 /* enable, etc */
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#define BCE_DMA_RXADDR 0x0214 /* rx ring base address */
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#define BCE_DMA_RXDPTR 0x0218 /* last descriptor */
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#define BCE_DMA_RXSTATUS 0x021C /* active desc, etc */
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/* receive status bits */
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#define RS_CD_MASK 0x0fff /* current descriptor pointer */
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#define RS_DMA_IDLE 0x2000 /* DMA is idle */
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#define RS_ERROR 0xf0000 /* had an error */
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/* Ethernet MAC control registers */
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#define BCE_RX_CTL 0x0400 /* receive config */
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/* config bits */
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#define ERC_DB 0x00000001 /* disable broadcast */
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#define ERC_AM 0x00000002 /* rx all multicast */
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#define ERC_PE 0x00000008 /* promiscuous enable */
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#define BCE_RX_MAX 0x0404 /* max packet length */
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#define BCE_TX_MAX 0x0408
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#define BCE_MI_CTL 0x0410
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#define BCE_MI_COMM 0x0414
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#define BCE_MI_STS 0x041C
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/* mii status bits */
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#define BCE_MIINTR 0x00000001 /* mii mdio interrupt */
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#define BCE_FILT_LOW 0x0420 /* mac low 4 bytes */
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#define BCE_FILT_HI 0x0424 /* mac hi 2 bytes */
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#define BCE_FILT_CTL 0x0428 /* packet filter ctrl */
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#define BCE_ENET_CTL 0x042C
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/* bits for mac control */
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#define EC_EE 0x00000001 /* emac enable */
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#define EC_ED 0x00000002 /* disable emac */
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#define EC_ES 0x00000004 /* soft reset emac */
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#define EC_EP 0x00000008 /* external phy */
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#define BCE_TX_CTL 0x0430
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/* bits for transmit control */
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#define EXC_FD 0x00000001 /* full duplex */
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#define BCE_TX_WATER 0x0434 /* tx watermark */
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/* statistics counters */
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#define BCE_RX_PKTS 0x058C
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/* SiliconBackplane registers */
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#define BCE_SBIMSTATE 0x0f90
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#define BCE_SBTMSTATELOW 0x0f98
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#define BCE_SBTMSTATEHI 0x0f9C
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#define SBTML_RESET 0x1 /* reset */
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#define SBTML_REJ 0x2 /* reject */
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#define SBTML_CLK 0x10000 /* clock enable */
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#define SBTML_FGC 0x20000 /* force gated clocks on */
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/* MI communication register */
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#define BCE_MICOMM_DATA 0x0000FFFF
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#define BCE_MIREG(x) ((x & 0x1F) << 18)
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#define BCE_MIPHY(x) ((x & 0x1F) << 23)
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/* Magic constants.... */
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#define BCE_MAGIC_PHYEMAC_BASE 0x1000
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#define BCE_MAGIC_PHY (BCE_MAGIC_PHYEMAC_BASE + 90)
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#define BCE_MAGIC_ENET0 (BCE_MAGIC_PHYEMAC_BASE + 79)
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#define BCE_MAGIC_ENET1 (BCE_MAGIC_PHYEMAC_BASE + 78)
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#define BCE_MAGIC_ENET2 (BCE_MAGIC_PHYEMAC_BASE + 81)
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#define BCE_MAGIC_ENET3 (BCE_MAGIC_PHYEMAC_BASE + 80)
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#define BCE_MAGIC_ENET4 (BCE_MAGIC_PHYEMAC_BASE + 83)
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#define BCE_MAGIC_ENET5 (BCE_MAGIC_PHYEMAC_BASE + 82)
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#define SBIM_MAGIC_ERRORBITS 0x60000
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