419 lines
16 KiB
C
419 lines
16 KiB
C
/* $NetBSD: czreg.h,v 1.2 2007/12/25 18:33:40 perry Exp $ */
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/*-
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* Copyright (c) 2000 Zembu Labs, Inc.
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* All rights reserved.
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*
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* Author: Jason R. Thorpe <thorpej@zembu.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Zembu Labs, Inc.
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* 4. Neither the name of Zembu Labs nor the names of its employees may
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* be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ZEMBU LABS, INC. ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WAR-
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* RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DIS-
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* CLAIMED. IN NO EVENT SHALL ZEMBU LABS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register and firmware communication definitions for the Cyclades
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* Z series of multi-port serial adapters.
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*/
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/*
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* The Cyclades-Z series is an intelligent multi-port serial controller
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* comprised of:
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*
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* - PLX PCI9060ES PCI bus interface
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* - Xilinx XC5204 FPGA
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* - IDT R3052 MIPS CPU
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*
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* Communication is performed by modifying structures in board local
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* RAM or in host RAM. We define offsets into these structures so
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* that either access method may be used.
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*
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* The Cyclades-Z comes in three basic flavors:
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*
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* - Cyclades-8Zo rev 1 -- This is an older 8-port board with no
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* FPGA.
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*
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* - Cyclades-8Zo rev 2 -- This is the newer 8-port board, which
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* uses an octopus cable.
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*
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* - Cyclades-Ze -- This is the top-of-the-line of the Cyclades
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* multiport serial controllers. It uses a SCSI-2 cable to
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* connect the card to a rack-mountable serial expansion box
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* (1U high). Each box has 16 RJ45 serial ports, and up to
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* 4 boxes can be chained together, for a total of 64 ports.
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* Up to 2 boxes can be used without an extra power supply.
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* Boxes 3 and 4 require their own external power supply,
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* otherwise the firmware will refuse to start (as it cannot
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* communicate with the UARTs in the boxes).
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*
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* The 8Zo flavors have not been tested, tho the programming interface
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* is identical (except for the firmware load phase of the 8Zo rev 1;
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* no FPGA load is done in that case), so they should work.
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*/
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/*
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* PLX Local Address Base values for the board RAM and FPGA regsiters.
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*
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* These values are specific to the Cyclades-Z.
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*/
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#define LOCAL_ADDR0_RAM (0x00000000 | LASBA_ENABLE)
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#define LOCAL_ADDR0_FPGA (0x14000000 | LASBA_ENABLE)
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/*
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* PLX Mailbox0 values.
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*
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* These values are specific to the Cyclades-Z.
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*/
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#define MAILBOX0_8Zo_V1 0 /* Cyclades-8Zo ver. 1 */
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#define MAILBOX0_8Zo_V2 1 /* Cyclades-8Zo ver. 2 */
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#define MAILBOX0_Ze_V1 2 /* Cyclades-Ze ver. 1 */
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/*
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* Bits in the PLX INIT_CTRL register.
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*
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* These values are specific to the Cyclades-Z.
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*/
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#define CONTROL_FPGA_LOADED CONTROL_GPI
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/*
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* FPGA registers on the 8Zo boards.
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*/
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#define FPGA_ID 0x00 /* FPGA ID */
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#define FPGA_VERSION 0x04 /* FPGA version */
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#define FPGA_CPU_START 0x08 /* CPU start */
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#define FPGA_CPU_STOP 0x0c /* CPU stop */
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#define FPGA_MISC 0x10 /* Misc. register */
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#define FPGA_IDT_MODE 0x14 /* IDT MIPS R3000 mode */
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#define FPGA_UART_IRQ_STAT 0x18 /* UART interrupt status */
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#define FPGA_CLEAR_TIMER0_IRQ 0x1c /* clear timer 0 interrupt */
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#define FPGA_CLEAR_TIMER1_IRQ 0x20 /* clear timer 1 interrupt */
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#define FPGA_CLEAR_TIMER2_IRQ 0x24 /* clear timer 3 interrupt */
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#define FPGA_TEST 0x28 /* test register */
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#define FPGA_TEST_COUNT 0x2c /* test count register */
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#define FPGA_TIMER_SELECT 0x30 /* timer select */
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#define FPGA_PR_UART_IRQ_STAT 0x34 /* prioritized UART interrupt status */
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#define FPGA_RAM_WAIT_STATE 0x38 /* RAM wait state */
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#define FPGA_UART_WAIT_STATE 0x3c /* UART wait state */
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#define FPGA_TIMER_WAIT_STATE 0x40 /* timer wait state */
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#define FPGA_ACK_WAIT_STATE 0x44 /* ACK wait state */
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/*
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* FPGA registers on the Ze boards. Note that the important registers
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* (FPGA_ID, FPGA_VERSION, FPGA_CPU_START, FPGA_CPU_STOP) are all in the
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* same place as on the 8Zo boards, and have the same meanings.
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*/
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#define FPGA_ZE_ID 0x00 /* FPGA ID */
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#define FPGA_ZE_VERSION 0x04 /* FPGA version */
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#define FPGA_ZE_CPU_START 0x08 /* CPU start */
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#define FPGA_ZE_CPU_STOP 0x0c /* CPU stop */
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#define FPGA_ZE_CTRL 0x10 /* CPU control */
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#define FPGA_ZE_ZBUS_WAIT 0x14 /* Z-Bus wait state */
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#define FPGA_ZE_TIMER_DIV 0x18 /* timer divisor */
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#define FPGA_ZE_TIMER_IRQ_ACK 0x1c /* timer interrupt ACK */
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/*
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* Values for FPGA ID.
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*/
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#define FPGA_ID_8Zo_V1 0x95 /* Cyclades-8Zo ver. 1 */
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#define FPGA_ID_8Zo_V2 0x84 /* Cyclades-8Zo ver. 2 */
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#define FPGA_ID_Ze_V1 0x89 /* Cyclades-Ze ver. 1 */
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/*
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* Values for Cyclades-Ze timer divisor.
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*/
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#define ZE_TIMER_DIV_1M 0x00
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#define ZE_TIMER_DIV_256K 0x01
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#define ZE_TIMER_DIV_128K 0x02
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#define ZE_TIMER_DIV_32K 0x03
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/*
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* Firmware interface starts here.
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*
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* These values are valid for the following Cyclades-Z firmware:
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*
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* @(#) Copyright (c) Cyclades Corporation, 1996, 1999
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* @(#) ZFIRM Cyclades-Z/PCI Firmware V_3.3.1 09/24/99
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*/
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/*
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* Structure of the firmware header.
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*/
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#define ZFIRM_MAX_BLOCKS 16 /* max. # of firmware/FPGA blocks */
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struct zfirm_header {
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u_int8_t zfh_name[64];
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u_int8_t zfh_date[32];
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u_int8_t zfh_aux[32];
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u_int32_t zfh_nconfig;
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u_int32_t zfh_configoff;
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u_int32_t zfh_nblocks;
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u_int32_t zfh_blockoff;
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u_int32_t zfh_reserved[9];
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} __packed;
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struct zfirm_config {
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u_int8_t zfc_name[64];
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u_int32_t zfc_mailbox;
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u_int32_t zfc_function;
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u_int32_t zfc_nblocks;
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u_int32_t zfc_blocklist[ZFIRM_MAX_BLOCKS];
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} __packed;
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#define ZFC_FUNCTION_NORMAL 0 /* normal operation */
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#define ZFC_FUNCTION_TEST 1 /* test mode operation */
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struct zfirm_block {
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u_int32_t zfb_type;
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u_int32_t zfb_fileoff;
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u_int32_t zfb_ramoff;
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u_int32_t zfb_size;
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} __packed;
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#define ZFB_TYPE_FIRMWARE 0 /* MIPS firmware */
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#define ZFB_TYPE_FPGA 1 /* FPGA code */
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#define ZFIRM_MAX_CHANNELS 64 /* max. # channels per board */
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/*
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* Firmware ID structure, which the firmware sets up after it boots.
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*/
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#define ZFIRM_SIG_OFF 0x00000180 /* offset of signature in board RAM */
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#define ZFIRM_CTRLADDR_OFF 0x00000184 /* offset of offset of control
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structure */
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#define ZFIRM_SIG 0x5557465A /* ZFIRM signature */
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#define ZFIRM_HLT 0x59505B5C /* Halt due to power problem */
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#define ZFIRM_RST 0x56040674 /* Firmware reset */
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/*
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* The firmware control structures are made up of the following:
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*
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* BOARD CONTROL (64 bytes)
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* CHANNEL CONTROL (96 bytes * ZFIRM_MAX_CHANNELS)
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* BUFFER CONTROL (64 bytes * ZFIRM_MAX_CHANNELS)
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*/
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#define ZFIRM_BRDCTL_SIZE 64
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#define ZFIRM_CHNCTL_SIZE 96
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#define ZFIRM_BUFCTL_SIZE 64
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#define ZFIRM_CHNCTL_OFF(chan, reg) \
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(ZFIRM_BRDCTL_SIZE + ((chan) * ZFIRM_CHNCTL_SIZE) + (reg))
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#define ZFIRM_BUFCTL_OFF(chan, reg) \
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(ZFIRM_CHNCTL_OFF(ZFIRM_MAX_CHANNELS, 0) + \
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((chan) * ZFIRM_BUFCTL_SIZE) + (reg))
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/*
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* Offsets in the BOARD CONTROL structure.
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*/
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/* static info provided by MIPS */
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#define BRDCTL_NCHANNEL 0x00 /* number of channels */
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#define BRDCTL_FWVERSION 0x04 /* firmware version */
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/* static info provided by driver */
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#define BRDCTL_C_OS 0x08 /* operating system ID */
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#define BRDCTL_DRVERSION 0x0c /* driver version */
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/* board control area */
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#define BRDCTL_INACTIVITY 0x10 /* inactivity control */
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/* host to firmware commands */
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#define BRDCTL_HCMD_CHANNEL 0x14 /* channel number */
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#define BRDCTL_HCMD_PARAM 0x18 /* parameter */
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/* firmware to host commands */
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#define BRDCTL_FWCMD_CHANNEL 0x1c /* channel number */
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#define BRDCTL_FWCMD_PARAM 0x20 /* parameter */
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#define BRDCTL_INT_QUEUE_OFF 0x24 /* offset to INT_QUEUE structure */
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/*
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* Offsets in the CHANNEL CONTROL structure.
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*/
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#define CHNCTL_OP_MODE 0x00 /* operation mode */
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#define CHNCTL_INTR_ENABLE 0x04 /* interrupt making for UART */
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#define CHNCTL_SW_FLOW 0x08 /* SW flow control */
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#define CHNCTL_FLOW_STATUS 0x0c /* output flow status */
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#define CHNCTL_COMM_BAUD 0x10 /* baud rate -- numerically specified */
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#define CHNCTL_COMM_PARITY 0x14 /* parity */
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#define CHNCTL_COMM_DATA_L 0x18 /* data length/stop */
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#define CHNCTL_COMM_FLAGS 0x1c /* other flags */
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#define CHNCTL_HW_FLOW 0x20 /* HW flow control */
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#define CHNCTL_RS_CONTROL 0x24 /* RS-232 outputs */
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#define CHNCTL_RS_STATUS 0x28 /* RS-232 inputs */
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#define CHNCTL_FLOW_XON 0x2c /* XON character */
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#define CHNCTL_FLOW_XOFF 0x30 /* XOFF character */
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#define CHNCTL_HW_OVERFLOW 0x34 /* HW overflow counter */
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#define CHNCTL_SW_OVERFLOW 0x38 /* SW overflow counter */
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#define CHNCTL_COMM_ERROR 0x3c /* frame/parity error counter */
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#define CHNCTL_ICHAR 0x40 /* special interrupt character */
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/*
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* Offsets in the BUFFER CONTROL structure.
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*/
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#define BUFCTL_FLAG_DMA 0x00 /* buffers are in Host memory */
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#define BUFCTL_TX_BUFADDR 0x04 /* address of Tx buffer */
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#define BUFCTL_TX_BUFSIZE 0x08 /* size of Tx buffer */
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#define BUFCTL_TX_THRESHOLD 0x0c /* Tx low water mark */
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#define BUFCTL_TX_GET 0x10 /* tail index Tx buf */
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#define BUFCTL_TX_PUT 0x14 /* head index Tx buf */
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#define BUFCTL_RX_BUFADDR 0x18 /* address of Rx buffer */
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#define BUFCTL_RX_BUFSIZE 0x1c /* size of Rx buffer */
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#define BUFCTL_RX_THRESHOLD 0x20 /* Rx high water mark */
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#define BUFCTL_RX_GET 0x24 /* tail index Rx buf */
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#define BUFCTL_RX_PUT 0x28 /* head index Rx buf */
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/* Values for operating system ID (BOARD CONTROL) */
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#define C_OS_SVR3 0x00000010 /* generic SVR3 */
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#define C_OS_XENIX 0x00000011 /* SCO XENIX */
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#define C_OS_SCO 0x00000012 /* SCO SVR3 */
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#define C_OS_SVR4 0x00000020 /* generic SVR4 */
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#define C_OS_UXWARE 0x00000021 /* UnixWare */
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#define C_OS_LINUX 0x00000030 /* Linux */
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#define C_OS_SOLARIS 0x00000040 /* Solaris */
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#define C_OS_BSD 0x00000050 /* generic BSD */
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#define C_OS_DOS 0x00000070 /* generic DOS */
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#define C_OS_NT 0x00000080 /* Windows NT */
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#define C_OS_OS2 0x00000090 /* IBM OS/2 */
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#define C_OS_MACOS 0x000000a0 /* MacOS */
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#define C_OS_AIX 0x000000b0 /* IBM AIX */
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/* Values for op_mode (CHANNEL CONTROL) */
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#define C_CH_DISABLE 0x00000000 /* channel is disabled */
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#define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */
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#define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */
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#define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */
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#define C_CH_LOOPBACK 0x00000004 /* Loopback mode */
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/* Values for comm_parity (CHANNEL CONTROL) */
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#define C_PR_NONE 0x00000000 /* None */
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#define C_PR_ODD 0x00000001 /* Odd */
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#define C_PR_EVEN 0x00000002 /* Even */
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#define C_PR_MARK 0x00000004 /* Mark */
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#define C_PR_SPACE 0x00000008 /* Space */
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#define C_PR_PARITY 0x000000ff
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#define C_PR_DISCARD 0x00000100 /* discard char with
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frame/parity error */
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#define C_PR_IGNORE 0x00000200 /* ignore frame/par error */
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/* Values for comm_data_l (CHANNEL CONTROL) */
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#define C_DL_CS5 0x00000001
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#define C_DL_CS6 0x00000002
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#define C_DL_CS7 0x00000004
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#define C_DL_CS8 0x00000008
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#define C_DL_CS 0x0000000f
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#define C_DL_1STOP 0x00000010
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#define C_DL_15STOP 0x00000020
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#define C_DL_2STOP 0x00000040
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#define C_DL_STOP 0x000000f0
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/* Values for intr_enable (CHANNEL CONTROL) */
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#define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */
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#define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */
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#define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */
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#define C_IN_TXFEMPTY 0x00000004 /* tx buffer + FIFO +
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shift reg. empty */
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#define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */
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#define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */
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#define C_IN_MDCD 0x00000100 /* modem DCD change */
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#define C_IN_MDSR 0x00000200 /* modem DSR change */
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#define C_IN_MRI 0x00000400 /* modem RI change */
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#define C_IN_MCTS 0x00000800 /* modem CTS change */
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#define C_IN_RXBRK 0x00001000 /* Break received */
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#define C_IN_PR_ERROR 0x00002000 /* parity error */
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#define C_IN_FR_ERROR 0x00004000 /* frame error */
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#define C_IN_OVR_ERROR 0x00008000 /* overrun error */
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#define C_IN_RXOFL 0x00010000 /* RX buffer overflow */
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#define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */
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#define C_IN_MRTS 0x00040000 /* modem RTS drop */
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#define C_IN_ICHAR 0x00080000 /* special intr. char
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received */
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/* Values for flow control (CHANNEL CONTROL) */
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#define C_FL_OXX 0x00000001 /* output Xon/Xoff flow
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control */
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#define C_FL_IXX 0x00000002 /* input Xon/Xoff flow
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control */
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#define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */
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#define C_FL_SWFLOW 0x0000000f
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/* Values for flow status (CHANNEL CONTROL) */
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#define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer
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or UART */
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#define C_FS_SENDING 0x00000001 /* UART is sending data */
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#define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received
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Xoff */
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/* Values for RS-232 signals (CHANNEL CONTROL) */
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#define C_RS_PARAM 0x80000000 /* indicates presence of
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parameter in IOCTL command */
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#define C_RS_RTS 0x00000001 /* RTS */
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#define C_RS_DTR 0x00000004 /* DTR */
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#define C_RS_DCD 0x00000100 /* CD */
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#define C_RS_DSR 0x00000200 /* DSR */
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#define C_RS_RI 0x00000400 /* RI */
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#define C_RS_CTS 0x00000800 /* CTS */
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/* Commands Host <--> Board */
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#define C_CM_RESET 0x01 /* resets/flushes buffers */
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#define C_CM_IOCTL 0x02 /* re-reads CH_CTRL */
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#define C_CM_IOCTLW 0x03 /* re-reads CH_CTRL, intr when done */
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#define C_CM_IOCTLM 0x04 /* RS-232 outputs change */
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#define C_CM_SENDXOFF 0x10 /* sends Xoff */
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#define C_CM_SENDXON 0x11 /* sends Xon */
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#define C_CM_CLFLOW 0x12 /* Clears flow control (resume) */
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#define C_CM_SENDBRK 0x41 /* sends break */
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#define C_CM_INTBACK 0x42 /* Interrupt back */
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#define C_CM_SET_BREAK 0x43 /* Tx break on */
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#define C_CM_CLR_BREAK 0x44 /* Tx break off */
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#define C_CM_CMD_DONE 0x45 /* Previous command done */
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#define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */
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#define C_CM_TINACT 0x51 /* sets inactivity detection */
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#define C_CM_IRQ_ENBL 0x52 /* enables generation of interrupts */
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#define C_CM_IRQ_DSBL 0x53 /* disables generation of interrupts */
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#define C_CM_ACK_ENBL 0x54 /* enables acknolowdged interrupt
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mode */
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#define C_CM_ACK_DSBL 0x55 /* disables acknolowdged intr mode */
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#define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */
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#define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */
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#define C_CM_Q_ENABLE 0x58 /* enables queue access from the
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driver */
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#define C_CM_Q_DISABLE 0x59 /* disables queue access from the
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driver */
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#define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */
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#define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */
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#define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */
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#define C_CM_RXNNDT 0x63 /* rx no new data timeout */
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#define C_CM_TXFEMPTY 0x64 /* Tx buffer, FIFO and shift reg.
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are empty */
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#define C_CM_ICHAR 0x65 /* Special Interrupt Character
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received */
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#define C_CM_MDCD 0x70 /* modem DCD change */
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#define C_CM_MDSR 0x71 /* modem DSR change */
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#define C_CM_MRI 0x72 /* modem RI change */
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#define C_CM_MCTS 0x73 /* modem CTS change */
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#define C_CM_MRTS 0x74 /* modem RTS drop */
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#define C_CM_RXBRK 0x84 /* Break received */
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#define C_CM_PR_ERROR 0x85 /* Parity error */
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#define C_CM_FR_ERROR 0x86 /* Frame error */
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#define C_CM_OVR_ERROR 0x87 /* Overrun error */
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#define C_CM_RXOFL 0x88 /* RX buffer overflow */
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#define C_CM_CMDERROR 0x90 /* command error */
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#define C_CM_FATAL 0x91 /* fatal error */
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#define C_CM_HW_RESET 0x92 /* reset board */
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