96 lines
3.7 KiB
C
96 lines
3.7 KiB
C
/* $NetBSD: ebusreg.h,v 1.1 1999/06/04 13:29:13 mrg Exp $ */
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/*
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* Copyright (c) 1999 Matthew R. Green
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _SPARC64_DEV_EBUSREG_H_
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#define _SPARC64_DEV_EBUSREG_H_
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/*
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* UltraSPARC `ebus'
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*
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* The `ebus' bus is designed to plug traditional PC-ISA devices into
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* an SPARC system with as few costs as possible, without sacrificing
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* to performance. Typically, it is implemented in the PCIO IC from
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* SME, which also implements a `hme-compatible' PCI network device
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* (`network'). The ebus has 4 DMA channels, similar to the DMA seen
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* in the ESP SCSI DMA.
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*
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* Typical UltraSPARC systems have a NatSemi SuperIO IC to provide
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* serial ports for the keyboard and mouse (`se'), floppy disk
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* controller (`fdthree'), parallel port controller (`bpp') connected
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* to the ebus, and a PCI-IDE controller (connected directly to the
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* PCI bus, of course), as well as a Siemens Nixdorf SAB82532 dual
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* channel serial controller (`su' providing ttya and ttyb), an MK48T59
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* EEPROM/clock controller (also where the idprom, including the
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* ethernet address, is located), the audio system (`SUNW,CS4231', same
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* as other UltraSPARC and some SPARC systems), and other various
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* internal devices found on traditional SPARC systems such as the
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* `power', `flashprom', etc., devices.
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*
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* The ebus uses an interrupt mapping scheme similar to PCI, though
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* the actual structures are different.
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*/
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/*
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* ebus PROM structures
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*/
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struct ebus_regs {
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u_int32_t hi; /* high bits of physaddr */
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u_int32_t lo;
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u_int32_t size;
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};
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#define EBUS_PADDR_FROM_REG(reg) ((((paddr_t)((reg)->hi)) << 32UL) | ((paddr_t)(reg)->lo))
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struct ebus_ranges {
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u_int32_t child_hi; /* child high phys addr */
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u_int32_t child_lo; /* child low phys addr */
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u_int32_t phys_hi; /* parent high phys addr */
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u_int32_t phys_mid; /* parent mid phys addr */
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u_int32_t phys_lo; /* parent low phys addr */
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u_int32_t size;
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};
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struct ebus_interrupt_map {
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u_int32_t hi; /* high phys addr mask */
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u_int32_t lo; /* low phys addr mask */
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u_int32_t intr; /* interrupt mask */
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int32_t cnode; /* child node */
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u_int32_t cintr; /* child interrupt */
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};
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struct ebus_interrupt_map_mask {
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u_int32_t hi; /* high phys addr */
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u_int32_t lo; /* low phys addr */
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u_int32_t intr; /* interrupt */
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};
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#endif /* _SPARC64_DEV_EBUSREG_H_ */
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