660 lines
13 KiB
C
660 lines
13 KiB
C
/* $NetBSD: zl10353.c,v 1.5 2017/06/01 02:45:10 chs Exp $ */
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/*-
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* Copyright (c) 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jukka Ruohonen.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: zl10353.c,v 1.5 2017/06/01 02:45:10 chs Exp $");
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#include <sys/param.h>
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#include <sys/kmem.h>
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#include <sys/module.h>
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#include <dev/dtv/dtvif.h>
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#include <dev/i2c/i2cvar.h>
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#include <dev/i2c/zl10353reg.h>
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#include <dev/i2c/zl10353var.h>
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/*
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* Zarlink ZL10353 demodulator (now known as Intel CE623x).
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*
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* An incomplete datasheet:
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*
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* Intel Corporation: CE6230 - COFDM demodulator with
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* USB interface for PC-TV. Data Sheet, Revision 1.1.
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* March 29, 2007.
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*/
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static int zl10353_probe(struct zl10353 *);
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static int zl10353_read(struct zl10353 *, uint8_t, uint8_t *);
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static int zl10353_write(struct zl10353 *, uint8_t, uint8_t);
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static int zl10353_reset(struct zl10353 *, bool);
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static int zl10353_set_agc(struct zl10353 *,
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const struct dvb_frontend_parameters *);
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static int zl10353_set_bw(struct zl10353 *, fe_bandwidth_t);
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static int zl10353_set_rate(struct zl10353 *);
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static int zl10353_set_freq(struct zl10353 *);
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static int zl10353_set_tps(struct zl10353 *,
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const struct dvb_frontend_parameters *);
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static int zl10353_get_guard(fe_guard_interval_t, uint16_t *);
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static int zl10353_get_mode(fe_transmit_mode_t, uint16_t *);
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static int zl10353_get_fec(fe_code_rate_t, bool, uint16_t *);
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static int zl10353_get_modulation(fe_modulation_t, uint16_t *);
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static int zl10353_get_hier(fe_hierarchy_t, uint16_t *);
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struct zl10353 *
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zl10353_open(device_t parent, i2c_tag_t i2c, i2c_addr_t addr)
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{
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struct zl10353 *zl;
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zl = kmem_zalloc(sizeof(*zl), KM_SLEEP);
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zl->zl_i2c = i2c;
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zl->zl_i2c_addr = addr;
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zl->zl_parent = parent;
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zl->zl_freq = ZL10353_DEFAULT_INPUT_FREQ;
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zl->zl_clock = ZL10353_DEFAULT_CLOCK_MHZ;
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if (zl10353_reset(zl, true) != 0) {
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zl10353_close(zl);
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return NULL;
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}
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if (zl10353_probe(zl) != 0) {
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zl10353_close(zl);
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return NULL;
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}
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return zl;
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}
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void
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zl10353_close(struct zl10353 *zl)
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{
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kmem_free(zl, sizeof(*zl));
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}
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static int
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zl10353_probe(struct zl10353 *zl)
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{
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uint8_t val;
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int rv;
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if ((rv = zl10353_read(zl, ZL10353_REG_ID, &val)) != 0)
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return rv;
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switch (val) {
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case ZL10353_ID_CE6230:
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zl->zl_name = "Intel CE6230";
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break;
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case ZL10353_ID_CE6231:
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zl->zl_name = "Intel CE6231";
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break;
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case ZL10353_ID_ZL10353:
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zl->zl_name = "Zarlink ZL10353";
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break;
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default:
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aprint_error_dev(zl->zl_parent, "unknown chip 0x%02x\n", val);
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return ENOTSUP;
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}
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aprint_verbose_dev(zl->zl_parent, "found %s at i2c "
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"addr 0x%02x\n", zl->zl_name, zl->zl_i2c_addr);
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return 0;
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}
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static int
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zl10353_read(struct zl10353 *zl, uint8_t reg, uint8_t *valp)
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{
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static const i2c_op_t op = I2C_OP_READ;
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int rv;
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if ((rv = iic_acquire_bus(zl->zl_i2c, 0)) != 0)
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return rv;
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rv = iic_exec(zl->zl_i2c, op, zl->zl_i2c_addr, ®, 1, valp, 1, 0);
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iic_release_bus(zl->zl_i2c, 0);
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return rv;
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}
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static int
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zl10353_write(struct zl10353 *zl, uint8_t reg, uint8_t val)
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{
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static const i2c_op_t op = I2C_OP_WRITE;
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const uint8_t cmd[2] = { reg, val };
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int rv;
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if ((rv = iic_acquire_bus(zl->zl_i2c, 0)) != 0)
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return rv;
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rv = iic_exec(zl->zl_i2c, op, zl->zl_i2c_addr, cmd, 2, NULL, 0, 0);
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iic_release_bus(zl->zl_i2c, 0);
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return rv;
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}
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static int
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zl10353_reset(struct zl10353 *zl, bool hard)
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{
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size_t i = 0, len = 5;
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int rv;
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static const struct {
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uint8_t reg;
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uint8_t val;
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} reset[] = {
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{ 0x50, 0x03 }, /* Hard */
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{ 0x03, 0x44 },
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{ 0x44, 0x46 },
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{ 0x46, 0x15 },
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{ 0x15, 0x0f },
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{ 0x55, 0x80 }, /* Soft */
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{ 0xea, 0x01 },
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{ 0xea, 0x00 },
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};
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if (hard != true) {
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len = __arraycount(reset);
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i = 5;
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}
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while (i < len) {
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if ((rv = zl10353_write(zl, reset[i].reg, reset[i].val)) != 0)
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return rv;
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else {
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delay(100);
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}
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i++;
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}
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return 0;
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}
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void
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zl10353_get_devinfo(struct dvb_frontend_info *fi)
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{
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fi->type = FE_OFDM;
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fi->frequency_min = 174000000;
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fi->frequency_max = 862000000;
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fi->frequency_tolerance = 0;
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fi->frequency_stepsize = 166667;
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fi->caps |= FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
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FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_QPSK |
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FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_RECOVER |
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FE_CAN_MUTE_TS;
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fi->caps |= FE_CAN_FEC_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
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FE_CAN_QAM_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
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FE_CAN_HIERARCHY_AUTO;
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}
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int
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zl10353_set_params(struct zl10353 *zl,const struct dvb_frontend_parameters *fp)
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{
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int rv;
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/* 1. Soft reset. */
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if ((rv = zl10353_reset(zl, false)) != 0)
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return rv;
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/* 2. Set AGC. */
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if ((rv = zl10353_set_agc(zl, fp)) != 0)
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return rv;
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/* 3. Set bandwidth. */
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if ((rv = zl10353_set_bw(zl, fp->u.ofdm.bandwidth)) != 0)
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return rv;
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/* 4. Set nominal rate. */
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if ((rv = zl10353_set_rate(zl)) != 0)
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return rv;
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/* 5. Set input frequency. */
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if ((rv = zl10353_set_freq(zl)) != 0)
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return rv;
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/* 6. Set TPS parameters. */
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if ((rv = zl10353_set_tps(zl, fp)) != 0)
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return rv;
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return 0;
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}
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int
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zl10353_set_fsm(struct zl10353 *zl)
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{
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return zl10353_write(zl, ZL10353_REG_FSM, ZL10353_FSM_START);
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}
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int
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zl10353_set_gate(void *aux, bool enable)
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{
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uint8_t val = ZL10353_GATE_DISABLE;
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if (enable != false)
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val = ZL10353_GATE_ENABLE;
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return zl10353_write(aux, ZL10353_REG_GATE, val);
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}
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static int
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zl10353_set_agc(struct zl10353 *zl, const struct dvb_frontend_parameters *fp)
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{
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const struct dvb_ofdm_parameters *ofdm = &fp->u.ofdm;
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uint8_t val = ZL10353_AGC_TARGET_DEFAULT;
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int rv;
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if ((rv = zl10353_write(zl, ZL10353_REG_AGC_TARGET, val)) != 0)
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return rv;
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else {
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val = 0;
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}
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if (ofdm->guard_interval != GUARD_INTERVAL_AUTO)
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val |= ZL10353_AGC_CTRL_GUARD_NONAUTO;
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if (ofdm->transmission_mode != TRANSMISSION_MODE_AUTO)
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val |= ZL10353_AGC_CTRL_MODE_NONAUTO;
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return zl10353_write(zl, ZL10353_REG_AGC_CTRL, val);
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}
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static int
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zl10353_set_bw(struct zl10353 *zl, fe_bandwidth_t bw)
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{
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uint8_t val[3];
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int rv;
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switch (bw) {
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case BANDWIDTH_6_MHZ:
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val[0] = ZL10353_BW_1_6_MHZ;
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val[1] = ZL10353_BW_2_6_MHZ;
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val[2] = ZL10353_BW_3_6_MHZ;
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zl->zl_bw = 6;
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break;
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case BANDWIDTH_7_MHZ:
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val[0] = ZL10353_BW_1_7_MHZ;
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val[1] = ZL10353_BW_2_7_MHZ;
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val[2] = ZL10353_BW_3_7_MHZ;
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zl->zl_bw = 7;
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break;
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case BANDWIDTH_8_MHZ:
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val[0] = ZL10353_BW_1_8_MHZ;
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val[1] = ZL10353_BW_2_8_MHZ;
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val[2] = ZL10353_BW_3_8_MHZ;
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zl->zl_bw = 8;
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break;
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default:
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zl->zl_bw = 0;
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return EINVAL;
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}
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if ((rv = zl10353_write(zl, ZL10353_REG_BW_1, val[0])) != 0)
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return rv;
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if ((rv = zl10353_write(zl, ZL10353_REG_BW_2, val[1])) != 0)
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return rv;
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if ((rv = zl10353_write(zl, ZL10353_REG_BW_3, val[2])) != 0)
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return rv;
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return 0;
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}
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static int
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zl10353_set_rate(struct zl10353 *zl)
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{
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static const uint64_t c = 1497965625;
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uint64_t val;
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int rv;
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KASSERT(zl->zl_bw >= 6 && zl->zl_bw <= 8);
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KASSERT(zl->zl_clock > 0 && zl->zl_freq > 0);
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val = zl->zl_bw * c;
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val += zl->zl_clock >> 1;
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val /= zl->zl_clock;
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val = val & 0xffff;
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if ((rv = zl10353_write(zl, ZL10353_REG_RATE_1, val >> 8)) != 0)
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return rv;
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return zl10353_write(zl, ZL10353_REG_RATE_2, val & 0xff);
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}
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static int
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zl10353_set_freq(struct zl10353 *zl)
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{
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const uint16_t val = zl->zl_freq;
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int rv;
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if ((rv = zl10353_write(zl, ZL10353_REG_FREQ_1, val >> 8)) != 0)
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return rv;
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return zl10353_write(zl, ZL10353_REG_FREQ_2, val & 0xff);
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}
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static int
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zl10353_set_tps(struct zl10353 *zl, const struct dvb_frontend_parameters *fp)
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{
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const struct dvb_ofdm_parameters *ofdm = &fp->u.ofdm;
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uint16_t val = 0;
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int rv;
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if ((rv = zl10353_get_guard(ofdm->guard_interval, &val)) != 0)
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goto fail;
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if ((rv = zl10353_get_mode(ofdm->transmission_mode, &val)) != 0)
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goto fail;
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if ((rv = zl10353_get_fec(ofdm->code_rate_HP, true, &val)) != 0)
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goto fail;
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if ((rv = zl10353_get_fec(ofdm->code_rate_LP, false, &val)) != 0)
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goto fail;
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if ((rv = zl10353_get_modulation(ofdm->constellation, &val)) != 0)
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goto fail;
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if ((rv = zl10353_get_hier(ofdm->hierarchy_information, &val)) != 0)
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goto fail;
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if ((rv = zl10353_write(zl, ZL10353_REG_TPS_1, val >> 8)) != 0)
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goto fail;
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if ((rv = zl10353_write(zl, ZL10353_REG_TPS_2, val & 0xff)) != 0)
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goto fail;
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return 0;
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fail:
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aprint_error_dev(zl->zl_parent, "failed to set "
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"tps for %s (err %d)\n", zl->zl_name, rv);
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return rv;
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}
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static int
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zl10353_get_guard(fe_guard_interval_t fg, uint16_t *valp)
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{
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switch (fg) {
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case GUARD_INTERVAL_1_4:
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*valp |= ZL10353_TPS_GUARD_1_4;
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break;
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case GUARD_INTERVAL_1_8:
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*valp |= ZL10353_TPS_GUARD_1_8;
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break;
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case GUARD_INTERVAL_1_16:
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*valp |= ZL10353_TPS_GUARD_1_16;
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break;
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case GUARD_INTERVAL_1_32:
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*valp |= ZL10353_TPS_GUARD_1_32;
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break;
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case GUARD_INTERVAL_AUTO:
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*valp |= ZL10353_TPS_GUARD_AUTO;
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break;
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default:
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return EINVAL;
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}
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return 0;
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}
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static int
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zl10353_get_mode(fe_transmit_mode_t fm, uint16_t *valp)
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{
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switch (fm) {
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case TRANSMISSION_MODE_2K:
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*valp |= ZL10353_TPS_MODE_2K;
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break;
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case TRANSMISSION_MODE_8K:
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*valp |= ZL10353_TPS_MODE_8K;
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break;
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case TRANSMISSION_MODE_AUTO:
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*valp |= ZL10353_TPS_MODE_AUTO;
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break;
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default:
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return EINVAL;
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}
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return 0;
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}
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static int
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zl10353_get_fec(fe_code_rate_t fc, bool hp, uint16_t *valp)
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{
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uint16_t hpval = 0, lpval = 0;
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switch (fc) {
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case FEC_1_2:
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hpval = ZL10353_TPS_HP_FEC_1_2;
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lpval = ZL10353_TPS_LP_FEC_1_2;
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break;
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case FEC_2_3:
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hpval = ZL10353_TPS_HP_FEC_2_3;
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lpval = ZL10353_TPS_LP_FEC_2_3;
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break;
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case FEC_3_4:
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hpval = ZL10353_TPS_HP_FEC_3_4;
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lpval = ZL10353_TPS_LP_FEC_3_4;
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break;
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case FEC_5_6:
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hpval = ZL10353_TPS_HP_FEC_5_6;
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lpval = ZL10353_TPS_LP_FEC_5_6;
|
|
break;
|
|
|
|
case FEC_7_8:
|
|
hpval = ZL10353_TPS_HP_FEC_7_8;
|
|
lpval = ZL10353_TPS_LP_FEC_7_8;
|
|
break;
|
|
|
|
case FEC_AUTO:
|
|
hpval = ZL10353_TPS_HP_FEC_AUTO;
|
|
lpval = ZL10353_TPS_LP_FEC_AUTO;
|
|
break;
|
|
|
|
case FEC_NONE:
|
|
return EOPNOTSUPP;
|
|
|
|
default:
|
|
return EINVAL;
|
|
}
|
|
|
|
*valp |= (hp != false) ? hpval : lpval;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
zl10353_get_modulation(fe_modulation_t fm, uint16_t *valp)
|
|
{
|
|
|
|
switch (fm) {
|
|
|
|
case QPSK:
|
|
*valp |= ZL10353_TPS_MODULATION_QPSK;
|
|
break;
|
|
|
|
case QAM_16:
|
|
*valp |= ZL10353_TPS_MODULATION_QAM_16;
|
|
break;
|
|
|
|
case QAM_64:
|
|
*valp |= ZL10353_TPS_MODULATION_QAM_64;
|
|
break;
|
|
|
|
case QAM_AUTO:
|
|
*valp |= ZL10353_TPS_MODULATION_QAM_AUTO;
|
|
break;
|
|
|
|
default:
|
|
return EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
zl10353_get_hier(fe_hierarchy_t fh, uint16_t *valp)
|
|
{
|
|
|
|
switch (fh) {
|
|
|
|
case HIERARCHY_1:
|
|
*valp |= ZL10353_TPS_HIERARCHY_1;
|
|
break;
|
|
|
|
case HIERARCHY_2:
|
|
*valp |= ZL10353_TPS_HIERARCHY_2;
|
|
break;
|
|
|
|
case HIERARCHY_4:
|
|
*valp |= ZL10353_TPS_HIERARCHY_4;
|
|
break;
|
|
|
|
case HIERARCHY_NONE:
|
|
*valp |= ZL10353_TPS_HIERARCHY_NONE;
|
|
break;
|
|
|
|
case HIERARCHY_AUTO:
|
|
*valp |= ZL10353_TPS_HIERARCHY_AUTO;
|
|
break;
|
|
|
|
default:
|
|
return EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
fe_status_t
|
|
zl10353_get_status(struct zl10353 *zl)
|
|
{
|
|
const uint8_t lock = FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC;
|
|
fe_status_t fs = 0;
|
|
uint8_t val;
|
|
|
|
if (zl10353_read(zl, ZL10353_REG_STATUS_LOCK, &val) == 0) {
|
|
|
|
if ((val & ZL10353_STATUS_LOCK_ON) != 0)
|
|
fs |= FE_HAS_LOCK;
|
|
|
|
if ((val & ZL10353_STATUS_LOCK_CARRIER) != 0)
|
|
fs |= FE_HAS_CARRIER;
|
|
|
|
if ((val & ZL10353_STATUS_LOCK_VITERBI) != 0)
|
|
fs |= FE_HAS_VITERBI;
|
|
}
|
|
|
|
if (zl10353_read(zl, ZL10353_REG_STATUS_SYNC, &val) == 0) {
|
|
|
|
if ((val & ZL10353_STATUS_SYNC_ON) != 0)
|
|
fs |= FE_HAS_SYNC;
|
|
}
|
|
|
|
if (zl10353_read(zl, ZL10353_REG_STATUS_SIGNAL, &val) == 0) {
|
|
|
|
if ((val & ZL10353_STATUS_SIGNAL_ON) != 0)
|
|
fs |= FE_HAS_SIGNAL;
|
|
}
|
|
|
|
return ((fs & lock) != lock) ? fs & ~FE_HAS_LOCK : fs;
|
|
};
|
|
|
|
uint16_t
|
|
zl10353_get_signal_strength(struct zl10353 *zl)
|
|
{
|
|
uint8_t val1, val2;
|
|
|
|
if (zl10353_read(zl, ZL10353_REG_SIGSTR_1, &val1) != 0)
|
|
return 0;
|
|
|
|
if (zl10353_read(zl, ZL10353_REG_SIGSTR_2, &val2) != 0)
|
|
return 0;
|
|
|
|
return val1 << 10 | val2 << 2 | 0x03;
|
|
}
|
|
|
|
uint16_t
|
|
zl10353_get_snr(struct zl10353 *zl)
|
|
{
|
|
uint8_t val;
|
|
|
|
if (zl10353_read(zl, ZL10353_REG_SNR, &val) != 0)
|
|
return 0;
|
|
|
|
return (val << 8) | val;
|
|
}
|
|
|
|
MODULE(MODULE_CLASS_DRIVER, zl10353, "i2cexec");
|
|
|
|
static int
|
|
zl10353_modcmd(modcmd_t cmd, void *aux)
|
|
{
|
|
|
|
if (cmd != MODULE_CMD_INIT && cmd != MODULE_CMD_FINI)
|
|
return ENOTTY;
|
|
|
|
return 0;
|
|
}
|