296 lines
8.7 KiB
C
296 lines
8.7 KiB
C
/* $NetBSD: cpu.h,v 1.2 1996/05/21 15:32:53 oki Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1990, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah $Hdr: cpu.h 1.16 91/03/25$
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*
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* @(#)cpu.h 8.4 (Berkeley) 1/5/94
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*/
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#ifndef _X68K_CPU_H_
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#define _X68K_CPU_H_
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/*
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* Exported definitions unique to x68k/68k cpu support.
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*/
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/*
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* definitions of cpu-dependent requirements
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* referenced in generic code
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*/
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#define cpu_swapin(p) /* nothing */
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#define cpu_wait(p) /* nothing */
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#define cpu_swapout(p) /* nothing */
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/*
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* Arguments to hardclock and gatherstats encapsulate the previous
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* machine state in an opaque clockframe. One the x68k, we use
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* what the hardware pushes on an interrupt (frame format 0).
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*/
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struct clockframe {
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u_short sr; /* sr at time of interrupt */
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u_long pc; /* pc at time of interrupt */
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u_short vo; /* vector offset (4-word frame) */
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};
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#define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0)
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#define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)
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#define CLKF_PC(framep) ((framep)->pc)
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#if 0
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/* We would like to do it this way... */
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#define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0)
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#else
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/* but until we start using PSL_M, we have to do this instead */
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#define CLKF_INTR(framep) (0) /* XXX */
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#endif
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/*
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* Preempt the current process if in interrupt from user mode,
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* or after the current trap/syscall if in system mode.
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*/
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#define need_resched() { want_resched++; aston(); }
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/*
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* Give a profiling tick to the current process when the user profiling
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* buffer pages are invalid. On the x68k, request an ast to send us
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* through trap, marking the proc as needing a profiling tick.
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*/
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#define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); }
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/*
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* Notify the current process (p) that it has a signal pending,
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* process as soon as possible.
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*/
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#define signotify(p) aston()
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#define aston() (astpending++)
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int astpending; /* need to trap before returning to user mode */
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int want_resched; /* resched() was called */
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/*
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* simulated software interrupt register
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*/
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extern unsigned char ssir;
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#define SIR_NET 0x1
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#define SIR_CLOCK 0x2
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#define SIR_SERIAL 0x4
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#define SIR_KBD 0x8
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#define siroff(x) ssir &= ~(x)
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#define setsoftnet() ssir |= SIR_NET
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#define setsoftclock() ssir |= SIR_CLOCK
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#define setsoftserial() ssir |= SIR_SERIAL
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#define setsoftkbd() ssir |= SIR_KBD
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CONSDEV 1 /* dev_t: console terminal device */
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#define CPU_MAXID 2 /* number of valid machdep ids */
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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{ "console_device", CTLTYPE_STRUCT }, \
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}
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/*
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* The rest of this should probably be moved to ../x68k/x68kcpu.h,
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* although some of it could probably be put into generic 68k headers.
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*/
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/* values for machineid */
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/* values for mmutype (assigned for quick testing) */
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#define MMU_68040 -2 /* 68040 on-chip MMU */
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#define MMU_68030 -1 /* 68030 on-chip subset of 68851 */
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#define MMU_68851 1 /* Motorola 68851 */
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/* values for ectype */
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#define EC_PHYS -1 /* external physical address cache */
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#define EC_NONE 0 /* no external cache */
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#define EC_VIRT 1 /* external virtual address cache */
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/* values for cpuspeed (not really related to clock speed due to caches) */
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#define MHZ_8 1
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#define MHZ_16 2
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#define MHZ_25 3
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#define MHZ_33 4
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#define MHZ_50 6
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#ifdef _KERNEL
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extern int machineid, mmutype;
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extern char *intiolimit;
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/* autoconf.c */
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void configure __P((void));
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/* machdep.c */
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void dumpconf __P((void));
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void dumpsys __P((void));
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/* locore.s */
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struct pcb;
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struct fpframe;
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void savectx __P((struct pcb *));
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void switch_exit __P((struct proc *));
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void proc_trampoline __P((void));
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u_long getdfc __P((void));
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u_long getsfc __P((void));
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void loadustp __P((int));
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void m68881_save __P((struct fpframe *));
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void m68881_restore __P((struct fpframe *));
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void DCIS __P((void));
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void DCIU __P((void));
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void ICIA __P((void));
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void ICPA __P((void));
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void PCIA __P((void));
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void TBIA __P((void));
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void TBIS __P((vm_offset_t));
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void TBIAS __P((void));
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void TBIAU __P((void));
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#if defined(M68040) || defined(M68060)
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void DCFA __P((void));
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void DCFP __P((vm_offset_t));
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void DCFL __P((vm_offset_t));
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void DCPL __P((vm_offset_t));
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void DCPP __P((vm_offset_t));
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void ICPL __P((vm_offset_t));
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void ICPP __P((vm_offset_t));
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#endif
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/* sys_machdep.c */
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int cachectl __P((int, caddr_t, int));
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int dma_cachectl __P((caddr_t, int));
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/* vm_machdep.c */
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int kvtop __P((caddr_t));
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#ifdef GENERIC
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/* swapgeneric.c */
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void setconf __P((void));
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#endif /* GENERIC */
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#endif
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/* physical memory sections */
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#define INTIOBASE (0x00C00000)
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#define INTIOTOP (0x01000000)
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/*
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* Internal IO space:
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*
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* Ranges from 0xC00000 to 0x1000000 (IIOMAPSIZE).
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*
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* Internal IO space is mapped in the kernel from ``IODEVbase'' to
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* ``intiolimit'' (defined in locore.s). Since it is always mapped,
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* conversion between physical and kernel virtual addresses is easy.
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*/
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#define IIOPOFF(pa) ((int)(pa)-INTIOBASE)
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#define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 4mb */
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/*
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* External IO space:
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*/
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/*
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* 68851 and 68030 MMU
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*/
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#define PMMU_LVLMASK 0x0007
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#define PMMU_INV 0x0400
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#define PMMU_WP 0x0800
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#define PMMU_ALV 0x1000
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#define PMMU_SO 0x2000
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#define PMMU_LV 0x4000
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#define PMMU_BE 0x8000
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#define PMMU_FAULT (PMMU_WP|PMMU_INV)
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/*
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* 68040 MMU
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*/
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#define MMU4_RES 0x001
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#define MMU4_TTR 0x002
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#define MMU4_WP 0x004
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#define MMU4_MOD 0x010
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#define MMU4_CMMASK 0x060
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#define MMU4_SUP 0x080
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#define MMU4_U0 0x100
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#define MMU4_U1 0x200
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#define MMU4_GLB 0x400
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#define MMU4_BE 0x800
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/* 680X0 function codes */
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#define FC_USERD 1 /* user data space */
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#define FC_USERP 2 /* user program space */
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#define FC_SUPERD 5 /* supervisor data space */
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#define FC_SUPERP 6 /* supervisor program space */
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#define FC_CPU 7 /* CPU space */
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/* fields in the 68020 cache control register */
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#define IC_ENABLE 0x0001 /* enable instruction cache */
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#define IC_FREEZE 0x0002 /* freeze instruction cache */
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#define IC_CE 0x0004 /* clear instruction cache entry */
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#define IC_CLR 0x0008 /* clear entire instruction cache */
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/* additional fields in the 68030 cache control register */
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#define IC_BE 0x0010 /* instruction burst enable */
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#define DC_ENABLE 0x0100 /* data cache enable */
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#define DC_FREEZE 0x0200 /* data cache freeze */
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#define DC_CE 0x0400 /* clear data cache entry */
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#define DC_CLR 0x0800 /* clear entire data cache */
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#define DC_BE 0x1000 /* data burst enable */
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#define DC_WA 0x2000 /* write allocate */
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#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define CACHE_OFF (DC_CLR|IC_CLR)
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#define CACHE_CLR (CACHE_ON)
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#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
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#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
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/* 68040 cache control register */
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#define IC4_ENABLE 0x8000 /* instruction cache enable bit */
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#define DC4_ENABLE 0x80000000 /* data cache enable bit */
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#define CACHE4_ON (IC4_ENABLE|DC4_ENABLE)
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#define CACHE4_OFF (0)
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#endif /* _X68K_CPU_H_ */
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