2563 lines
62 KiB
C
2563 lines
62 KiB
C
/*
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* Copyright (c) 1993, 1994 Hellmuth Michaelis and Joerg Wunsch
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*
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* Copyright (C) 1992, 1993 Soeren Schmidt.
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*
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* All rights reserved.
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*
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* For the sake of compatibility, portions of this code regarding the
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* X server interface are taken from Soeren Schmidt's syscons driver.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by
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* Hellmuth Michaelis, Joerg Wunsch and Soeren Schmidt.
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* 4. The name authors may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*
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* @(#)pcvt_ext.c, 3.00, Last Edit-Date: [Sun Feb 27 17:04:52 1994]
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*
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*/
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/*---------------------------------------------------------------------------*
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*
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* pcvt_ext.c VT220 Driver Extended Support Routines
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* ------------------------------------------------------
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*
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* written by Hellmuth Michaelis, hm@hcshh.hcs.de and
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* Joerg Wunsch, joerg_wunsch@uriah.sax.de
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*
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* -hm splitting pcvt_sup.c
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* -hm adding 132 column support for S3 80c928 chipset
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* -hm support for keyboard scancode sets 1 and 2
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* -hm 132 col support for Cirrus 542x from Onno van der Linden
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* -jw/hm all ifdef's converted to if's
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* -hm applied patch from Szabolcs Szigeti for TVGA 8900B and
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* TVGA8900C to make the operating with 132 columns
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* -hm ------------ Release 3.00 --------------
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*
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*---------------------------------------------------------------------------*/
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#include "vt.h"
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#if NVT > 0
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#include "pcvt_hdr.h" /* global include */
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static int s3testwritable( void );
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/* storage to save video timing values of 80 columns text mode */
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static union {
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u_char generic[11];
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u_char et4000[11];
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u_char wd90c11[12];
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u_char tri9000[13];
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u_char v7_1024i[17];
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u_char s3_928[32];
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u_char cirrus[12];
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}
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savearea;
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static int regsaved = 0; /* registers are saved to savearea */
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/*---------------------------------------------------------------------------*
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*
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* Find out which video board we are running on, taken from:
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* Richard Ferraro: Programmers Guide to the EGA and VGA Cards
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* and from David E. Wexelblat's SuperProbe Version 1.0.
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* When a board is found, for which 132 column switching is
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* provided, the global variable "can_do_132col" is set to 1,
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* also the global variable vga_family is set to what we found.
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*
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* ###############################################################
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* ## THIS IS GETTING MORE AND MORE A LARGE SPAGHETTI HACK !!!! ##
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* ###############################################################
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*
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*---------------------------------------------------------------------------*/
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u_char
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vga_chipset(void)
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{
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u_char *ptr;
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u_char byte, oldbyte, old1byte, newbyte;
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#if PCVT_132GENERIC
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can_do_132col = 1; /* assumes everyone can do 132 col */
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#else
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can_do_132col = 0; /* assumes noone can do 132 col */
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#endif /* PCVT_132GENERIC */
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vga_family = VGA_F_NONE;
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/*---------------------------------------------------------------------------*
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* check for Western Digital / Paradise chipsets
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*---------------------------------------------------------------------------*/
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ptr = (u_char *)Crtat;
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if(color)
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ptr += (0xc007d - 0xb8000);
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else
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ptr += (0xc007d - 0xb0000);
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if((*ptr++ == 'V') && (*ptr++ == 'G') &&
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(*ptr++ == 'A') && (*ptr++ == '='))
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{
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int wd90c10;
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vga_family = VGA_F_WD;
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outb(addr_6845, 0x2b);
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oldbyte = inb(addr_6845+1);
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outb(addr_6845+1, 0xaa);
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newbyte = inb(addr_6845+1);
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outb(addr_6845+1, oldbyte);
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if(newbyte != 0xaa)
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return(VGA_PVGA); /* PVGA1A chip */
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outb(TS_INDEX, 0x12);
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oldbyte = inb(TS_DATA);
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outb(TS_DATA, oldbyte & 0xbf);
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newbyte = inb(TS_DATA) & 0x40;
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if(newbyte != 0)
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return(VGA_WD90C00); /* WD90C00 chip */
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outb(TS_DATA, oldbyte | 0x40);
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newbyte = inb(TS_DATA) & 0x40;
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if(newbyte == 0)
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return(VGA_WD90C00); /* WD90C00 chip */
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outb(TS_DATA, oldbyte);
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wd90c10 = 0;
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outb(TS_INDEX, 0x10);
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oldbyte = inb(TS_DATA);
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outb(TS_DATA, oldbyte & 0xfb);
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newbyte = inb(TS_DATA) & 0x04;
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if(newbyte != 0)
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wd90c10 = 1;
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outb(TS_DATA, oldbyte | 0x04);
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newbyte = inb(TS_DATA) & 0x04;
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if(newbyte == 0)
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wd90c10 = 1;
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outb(TS_DATA, oldbyte);
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if(wd90c10)
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return(VGA_WD90C10);
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else
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{
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can_do_132col = 1;
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return(VGA_WD90C11);
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}
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}
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/*---------------------------------------------------------------------------*
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* check for Trident chipsets
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*---------------------------------------------------------------------------*/
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outb(TS_INDEX, 0x0b);
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oldbyte = inb(TS_DATA);
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outb(TS_INDEX, 0x0b);
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outb(TS_DATA, 0x00);
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byte = inb(TS_DATA); /* chipset type */
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outb(TS_INDEX, 0x0e);
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old1byte = inb(TS_DATA);
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outb(TS_DATA, 0);
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newbyte = inb(TS_DATA);
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outb(TS_DATA, (old1byte ^ 0x02));
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outb(TS_INDEX, 0x0b);
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outb(TS_DATA, oldbyte);
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if((newbyte & 0x0f) == 0x02)
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{
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/* is a trident chip */
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vga_family = VGA_F_TRI;
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switch(byte)
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{
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case 0x01:
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return(VGA_TR8800BR);
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case 0x02:
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return(VGA_TR8800CS);
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case 0x03:
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can_do_132col = 1;
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return(VGA_TR8900B);
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case 0x04:
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case 0x13:
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/* Haven't tried, but should work */
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can_do_132col = 1;
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return(VGA_TR8900C);
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case 0x23:
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can_do_132col = 1;
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return(VGA_TR9000);
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case 0x33:
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return(VGA_TR8900CL);
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case 0x83:
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return(VGA_TR9200);
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case 0x93:
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return(VGA_TR9100);
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default:
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return(VGA_TRUNKNOWN);
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}
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}
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/*---------------------------------------------------------------------------*
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* check for Tseng Labs ET3000/4000 chipsets
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*---------------------------------------------------------------------------*/
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outb(GN_HERCOMPAT, 0x06);
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if(color)
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outb(GN_DMCNTLC, 0xa0);
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else
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outb(GN_DMCNTLM, 0xa0);
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/* read old value */
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if(color)
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inb(GN_INPSTAT1C);
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else
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inb(GN_INPSTAT1M);
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outb(ATC_INDEX, ATC_MISC);
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oldbyte = inb(ATC_DATAR);
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/* write new value */
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if(color)
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inb(GN_INPSTAT1C);
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else
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inb(GN_INPSTAT1M);
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outb(ATC_INDEX, ATC_MISC);
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newbyte = oldbyte ^ 0x10;
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outb(ATC_DATAW, newbyte);
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/* read back new value */
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if(color)
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inb(GN_INPSTAT1C);
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else
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inb(GN_INPSTAT1M);
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outb(ATC_INDEX, ATC_MISC);
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byte = inb(ATC_DATAR);
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/* write back old value */
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if(color)
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inb(GN_INPSTAT1C);
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else
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inb(GN_INPSTAT1M);
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outb(ATC_INDEX, ATC_MISC);
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outb(ATC_DATAW, oldbyte);
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if(byte == newbyte) /* ET3000 or ET4000 */
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{
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vga_family = VGA_F_TSENG;
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outb(addr_6845, CRTC_EXTSTART);
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oldbyte = inb(addr_6845+1);
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newbyte = oldbyte ^ 0x0f;
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outb(addr_6845+1, newbyte);
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byte = inb(addr_6845+1);
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outb(addr_6845+1, oldbyte);
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if(byte == newbyte)
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{
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can_do_132col = 1;
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return(VGA_ET4000);
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}
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else
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{
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return(VGA_ET3000);
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}
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}
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/*---------------------------------------------------------------------------*
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* check for Video7 VGA chipsets
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*---------------------------------------------------------------------------*/
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outb(TS_INDEX, TS_EXTCNTL); /* enable extensions */
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outb(TS_DATA, 0xea);
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outb(addr_6845, CRTC_STARTADRH);
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oldbyte = inb(addr_6845+1);
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outb(addr_6845+1, 0x55);
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newbyte = inb(addr_6845+1);
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outb(addr_6845, CRTC_V7ID); /* id register */
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byte = inb(addr_6845+1); /* read id */
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outb(addr_6845, CRTC_STARTADRH);
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outb(addr_6845+1, oldbyte);
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outb(TS_INDEX, TS_EXTCNTL); /* disable extensions */
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outb(TS_DATA, 0xae);
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if(byte == (0x55 ^ 0xea))
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{ /* is Video 7 */
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vga_family = VGA_F_V7;
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outb(TS_INDEX, TS_EXTCNTL); /* enable extensions */
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outb(TS_DATA, 0xea);
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outb(TS_INDEX, TS_V7CHIPREV);
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byte = inb(TS_DATA);
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outb(TS_INDEX, TS_EXTCNTL); /* disable extensions */
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outb(TS_DATA, 0xae);
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if(byte < 0xff && byte >= 0x80)
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return(VGA_V7VEGA);
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if(byte < 0x7f && byte >= 0x70)
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return(VGA_V7FWVR);
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if(byte < 0x5a && byte >= 0x50)
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return(VGA_V7V5);
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if(byte < 0x4a && byte > 0x40)
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{
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can_do_132col = 1;
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return(VGA_V71024I);
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}
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return(VGA_V7UNKNOWN);
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}
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/*---------------------------------------------------------------------------*
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* check for S3 chipsets
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*---------------------------------------------------------------------------*/
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outb(addr_6845, 0x38); /* reg 1 lock register */
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old1byte = inb(addr_6845+1); /* get old value */
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outb(addr_6845, 0x38);
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outb(addr_6845+1, 0x00); /* lock registers */
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if(s3testwritable() == 0) /* check if locked */
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{
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outb(addr_6845, 0x38);
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outb(addr_6845+1, 0x48); /* unlock registers */
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if(s3testwritable() == 1 ) /* check if unlocked */
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{
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vga_family = VGA_F_S3; /* FAMILY S3 */
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outb(addr_6845, 0x30); /* chip id/rev reg */
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byte = inb(addr_6845+1);
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switch(byte & 0xf0)
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{
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case 0x80:
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switch(byte & 0x0f)
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{
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case 0x01:
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outb(addr_6845, 0x38);
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outb(addr_6845+1, old1byte);
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return VGA_S3_911;
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case 0x02:
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outb(addr_6845, 0x38);
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outb(addr_6845+1, old1byte);
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return VGA_S3_924;
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default:
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outb(addr_6845, 0x38);
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outb(addr_6845+1, old1byte);
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return VGA_S3_UNKNOWN;
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}
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break;
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case 0xA0:
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outb(addr_6845, 0x38);
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outb(addr_6845+1, old1byte);
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return VGA_S3_80x;
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case 0x90:
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case 0xb0:
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outb(addr_6845, 0x38);
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outb(addr_6845+1, old1byte);
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can_do_132col = 1;
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return VGA_S3_928;
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default:
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outb(addr_6845, 0x38);
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outb(addr_6845+1, old1byte);
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return VGA_S3_UNKNOWN;
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}
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}
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}
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/*---------------------------------------------------------------------------*
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* check for Cirrus chipsets
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*---------------------------------------------------------------------------*/
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outb(TS_INDEX, 6);
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oldbyte = inb(TS_DATA);
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outb(TS_INDEX, 6);
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outb(TS_DATA, 0x12);
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outb(TS_INDEX, 6);
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newbyte = inb(TS_DATA);
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outb(addr_6845, 0x27);
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byte = inb(addr_6845 + 1);
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outb(TS_INDEX, 6);
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outb(TS_DATA, oldbyte);
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if (newbyte == 0x12) {
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vga_family = VGA_F_CIR;
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can_do_132col = 1;
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switch ((byte & 0xfc) >> 2) {
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case 0x22:
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switch (byte & 3) {
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case 0:
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return VGA_CL_GD5402;
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case 1:
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return VGA_CL_GD5402r1;
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case 2:
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return VGA_CL_GD5420;
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case 3:
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return VGA_CL_GD5420r1;
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}
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break;
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case 0x23:
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return VGA_CL_GD5422;
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case 0x25:
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return VGA_CL_GD5424;
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case 0x24:
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return VGA_CL_GD5426;
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case 0x26:
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return VGA_CL_GD5428;
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}
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}
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return(VGA_UNKNOWN);
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}
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/*---------------------------------------------------------------------------
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* test if index 35 lower nibble is writable (taken from SuperProbe 1.0)
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*---------------------------------------------------------------------------*/
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static int
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s3testwritable(void)
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{
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u_char old, new1, new2;
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outb(addr_6845, 0x35);
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old = inb(addr_6845+1); /* save */
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outb(addr_6845, 0x35);
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outb(addr_6845+1, (old & 0xf0)); /* write 0 */
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outb(addr_6845, 0x35);
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new1 = (inb(addr_6845+1)) & 0x0f; /* must read 0 */
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outb(addr_6845, 0x35);
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outb(addr_6845+1, (old | 0x0f)); /* write 1 */
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outb(addr_6845, 0x35);
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new2 = (inb(addr_6845+1)) & 0x0f; /* must read 1 */
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outb(addr_6845, 0x35);
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outb(addr_6845+1, old); /* restore */
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return((new1==0) && (new2==0x0f));
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}
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/*---------------------------------------------------------------------------*
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* return ptr to string describing vga type
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*---------------------------------------------------------------------------*/
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char *
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vga_string(int number)
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{
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static char *vga_tab[] = {
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"generic",
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"et4000",
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"et3000",
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"pvga1a",
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"wd90c00",
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"wd90c10",
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"wd90c11",
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"v7 vega",
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"v7 fast",
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"v7 ver5",
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"v7 1024i",
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"unknown v7",
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"tvga 8800br",
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"tvga 8800cs",
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"tvga 8900b",
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"tvga 8900c",
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"tvga 8900cl",
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"tvga 9000",
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"tvga 9100",
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"tvga 9200",
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"unknown trident",
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"s3 911",
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"s3 924",
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"s3 801/805",
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"s3 928",
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"unkown s3",
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"cl-gd5402",
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"cl-gd5402r1",
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"cl-gd5420",
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"cl-gd5420r1",
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"cl-gd5422",
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"cl-gd5424",
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"cl-gd5426",
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"cl-gd5428"
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};
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return(vga_tab[number]);
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|
}
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* toggle vga 80/132 column operation
|
|
*---------------------------------------------------------------------------*/
|
|
int
|
|
vga_col(struct video_state *svsp, int cols)
|
|
{
|
|
int ret = 0;
|
|
|
|
if(adaptor_type != VGA_ADAPTOR)
|
|
return(0);
|
|
|
|
switch(vga_type)
|
|
{
|
|
case VGA_ET4000:
|
|
ret = et4000_col(cols);
|
|
break;
|
|
|
|
case VGA_WD90C11:
|
|
ret = wd90c11_col(cols);
|
|
break;
|
|
case VGA_TR8900B:
|
|
case VGA_TR8900C:
|
|
case VGA_TR9000:
|
|
ret = tri9000_col(cols);
|
|
break;
|
|
|
|
case VGA_V71024I:
|
|
ret = v7_1024i_col(cols);
|
|
break;
|
|
|
|
case VGA_S3_928:
|
|
ret = s3_928_col(cols);
|
|
break;
|
|
|
|
case VGA_CL_GD5402:
|
|
case VGA_CL_GD5402r1:
|
|
case VGA_CL_GD5420:
|
|
case VGA_CL_GD5420r1:
|
|
case VGA_CL_GD5422:
|
|
case VGA_CL_GD5424:
|
|
case VGA_CL_GD5426:
|
|
case VGA_CL_GD5428:
|
|
ret = cl_gd542x_col(cols);
|
|
break;
|
|
|
|
default:
|
|
|
|
#if PCVT_132GENERIC
|
|
ret = generic_col(cols);
|
|
#endif /* PCVT_132GENERIC */
|
|
|
|
break;
|
|
}
|
|
|
|
if(ret == 0)
|
|
return(0); /* failed */
|
|
|
|
svsp->maxcol = cols;
|
|
|
|
return(1);
|
|
}
|
|
|
|
#if PCVT_132GENERIC
|
|
/*---------------------------------------------------------------------------*
|
|
* toggle 80/132 column operation for "generic" SVGAs
|
|
* NB: this is supposed to work on any (S)VGA as long as the monitor
|
|
* is able to sync down to 21.5 kHz horizontally. The resulting
|
|
* vertical frequency is only 50 Hz, so if there is some better board
|
|
* specific algorithm, we avoid using this generic one.
|
|
* REPORT ANY FAILURES SO WE CAN IMPROVE THIS
|
|
*---------------------------------------------------------------------------*/
|
|
|
|
#if PCVT_EXP_132COL
|
|
/*
|
|
* Some improved (i.e. higher scan rates) figures for the horizontal
|
|
* timing. USE AT YOUR OWN RISK, THIS MIGHT DAMAGE YOUR MONITOR DUE
|
|
* TO A LOSS OF HORIZONTAL SYNC!
|
|
* The figures have been tested with an ET3000 board along with a
|
|
* NEC MultiSync 3D monitor. If you are playing here, consider
|
|
* testing with several screen pictures (dark background vs. light
|
|
* background, even enlightening the border color may impact the
|
|
* result - you can do this e.g. by "scon -p black,42,42,42")
|
|
* Remember that all horizontal timing values must be dividable
|
|
* by 8! (The scheme below is taken so that nifty kernel hackers
|
|
* are able to patch the figures at run-time.)
|
|
*
|
|
* The actual numbers result in 23 kHz line scan and 54 Hz vertical
|
|
* scan.
|
|
*/
|
|
#endif /* PCVT_EXP_132COL */
|
|
|
|
int
|
|
generic_col(int cols)
|
|
{
|
|
u_char *sp;
|
|
u_char byte;
|
|
|
|
#if !PCVT_EXP_132COL
|
|
|
|
/* stable figures for any multisync monitor that syncs down to 22 kHz*/
|
|
static volatile u_short htotal = 1312;
|
|
static volatile u_short displayend = 1056;
|
|
static volatile u_short blankstart = 1072;
|
|
static volatile u_short syncstart = 1112;
|
|
static volatile u_short syncend = 1280;
|
|
|
|
#else /* PCVT_EXP_132COL */
|
|
|
|
/* reduced sync-pulse width and sync delays */
|
|
static volatile u_short htotal = 1232;
|
|
static volatile u_short displayend = 1056;
|
|
static volatile u_short blankstart = 1056;
|
|
static volatile u_short syncstart = 1104;
|
|
static volatile u_short syncend = 1168;
|
|
|
|
#endif /* PCVT_EXP_132COL */
|
|
|
|
vga_screen_off();
|
|
|
|
/* enable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
byte = inb(addr_6845+1);
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte & 0x7f);
|
|
|
|
if(cols == SCR_COL132) /* switch 80 -> 132 */
|
|
{
|
|
/* save state of board for 80 columns */
|
|
|
|
if(!regsaved)
|
|
{
|
|
regsaved = 1;
|
|
|
|
sp = savearea.generic;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
*sp++ = inb(GN_MISCOUTR); /* Misc output register */
|
|
}
|
|
|
|
/* setup chipset for 132 column operation */
|
|
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, (htotal / 8) - 5);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, (displayend / 8) - 1);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, blankstart / 8);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, ((syncend / 8) & 0x1f) | 0x80);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, syncstart / 8);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1,
|
|
(((syncend / 8) & 0x20) * 4)
|
|
| ((syncend / 8) & 0x1f));
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, 0x42);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, 0x01); /* 8 dot char clock */
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS); /* ATC Mode control */
|
|
outb(ATC_DATAW, 0x08); /* Line graphics disable */
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS); /* ATC Horizontal Pixel Panning */
|
|
outb(ATC_DATAW, 0x00);
|
|
|
|
/* Misc output register */
|
|
/* use the 28.322 MHz clock */
|
|
outb(GN_MISCOUTW, (inb(GN_MISCOUTR) & ~0x0c) | 4);
|
|
}
|
|
else /* switch 132 -> 80 */
|
|
{
|
|
if(!regsaved) /* failsafe */
|
|
{
|
|
/* disable access to first 7 CRTC registers */
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
vga_screen_on();
|
|
return(0);
|
|
}
|
|
|
|
sp = savearea.generic;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
outb(GN_MISCOUTW, *sp++); /* Misc output register */
|
|
}
|
|
|
|
/* disable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
|
|
vga_screen_on();
|
|
|
|
return(1);
|
|
}
|
|
#endif /* PCVT_132GENERIC */
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* toggle 80/132 column operation for ET4000 based boards
|
|
*---------------------------------------------------------------------------*/
|
|
int
|
|
et4000_col(int cols)
|
|
{
|
|
u_char *sp;
|
|
u_char byte;
|
|
|
|
vga_screen_off();
|
|
|
|
/* enable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
byte = inb(addr_6845+1);
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte & 0x7f);
|
|
|
|
if(cols == SCR_COL132) /* switch 80 -> 132 */
|
|
{
|
|
/* save state of board for 80 columns */
|
|
|
|
if(!regsaved)
|
|
{
|
|
regsaved = 1;
|
|
|
|
sp = savearea.et4000;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x34); /* 6845 Compatibility */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
*sp++ = inb(GN_MISCOUTR); /* Misc output register */
|
|
}
|
|
|
|
/* setup chipset for 132 column operation */
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, 0x9f);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, 0x83);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, 0x84);
|
|
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, 0x8b);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, 0x80);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, 0x42);
|
|
|
|
outb(addr_6845, 0x34); /* 6845 Compatibility */
|
|
outb(addr_6845+1, 0x0a);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, 0x01); /* 8 dot char clock */
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS); /* ATC Mode control */
|
|
outb(ATC_DATAW, 0x08); /* Line graphics disable */
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS); /* ATC Horizontal Pixel Panning */
|
|
outb(ATC_DATAW, 0x00);
|
|
|
|
/* Misc output register */
|
|
|
|
outb(GN_MISCOUTW, (inb(GN_MISCOUTR) & ~0x0c));
|
|
}
|
|
else /* switch 132 -> 80 */
|
|
{
|
|
if(!regsaved) /* failsafe */
|
|
{
|
|
/* disable access to first 7 CRTC registers */
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
vga_screen_on();
|
|
return(0);
|
|
}
|
|
|
|
sp = savearea.et4000;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x34); /* 6845 Compatibility */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
outb(GN_MISCOUTW, *sp++); /* Misc output register */
|
|
}
|
|
|
|
/* disable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
|
|
vga_screen_on();
|
|
|
|
return(1);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* toggle 80/132 column operation for WD/Paradise based boards
|
|
*
|
|
* when this card does 132 cols, the char map select register (TS_INDEX,
|
|
* TS_FONTSEL) function bits get REDEFINED. whoever did design this,
|
|
* please don't cross my way ever .......
|
|
*
|
|
*---------------------------------------------------------------------------*/
|
|
int
|
|
wd90c11_col(int cols)
|
|
{
|
|
|
|
#if !PCVT_BACKUP_FONTS
|
|
static unsigned char *sv_fontwd[NVGAFONTS];
|
|
#endif /* !PCVT_BACKUP_FONTS */
|
|
|
|
u_char *sp;
|
|
u_char byte;
|
|
int i;
|
|
|
|
vga_screen_off();
|
|
|
|
/* enable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
byte = inb(addr_6845+1);
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte & 0x7f);
|
|
|
|
/* enable access to WD/Paradise "control extensions" */
|
|
|
|
outb(GDC_INDEX, GDC_PR5GPLOCK);
|
|
outb(GDC_INDEX, 0x05);
|
|
outb(addr_6845, CRTC_PR10);
|
|
outb(addr_6845, 0x85);
|
|
outb(TS_INDEX, TS_UNLOCKSEQ);
|
|
outb(TS_DATA, 0x48);
|
|
|
|
if(cols == SCR_COL132) /* switch 80 -> 132 */
|
|
{
|
|
/* save state of board for 80 columns */
|
|
|
|
if(!regsaved)
|
|
{
|
|
regsaved = 1;
|
|
|
|
/* save current fonts */
|
|
|
|
#if !PCVT_BACKUP_FONTS
|
|
for(i = 0; i < totalfonts; i++)
|
|
{
|
|
if(vgacs[i].loaded)
|
|
{
|
|
if((sv_fontwd[i] =
|
|
(u_char *)malloc(32 * 256,
|
|
M_DEVBUF,
|
|
M_WAITOK))
|
|
== NULL)
|
|
printf("pcvt: no font buffer\n");
|
|
else
|
|
vga_move_charset(i,
|
|
sv_fontwd[i],
|
|
1);
|
|
}
|
|
else
|
|
{
|
|
sv_fontwd[i] = 0;
|
|
}
|
|
}
|
|
|
|
#endif /* !PCVT_BACKUP_FONTS */
|
|
|
|
sp = savearea.wd90c11;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x2e); /* misc 1 */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x2f); /* misc 2 */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(TS_INDEX, 0x10);/* Timing Sequencer */
|
|
*sp++ = inb(TS_DATA);
|
|
outb(TS_INDEX, 0x12);/* Timing Sequencer */
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
*sp++ = inb(GN_MISCOUTR); /* Misc output register */
|
|
}
|
|
|
|
/* setup chipset for 132 column operation */
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, 0x9c);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, 0x83);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, 0x84);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, 0x9f);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, 0x8a);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, 0x1c);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, 0x42);
|
|
|
|
outb(addr_6845, 0x2e); /* misc 1 */
|
|
outb(addr_6845+1, 0x04);
|
|
outb(addr_6845, 0x2f); /* misc 2 */
|
|
outb(addr_6845+1, 0x00);
|
|
|
|
outb(TS_INDEX, 0x10);/* Timing Sequencer */
|
|
outb(TS_DATA, 0x21);
|
|
outb(TS_INDEX, 0x12);/* Timing Sequencer */
|
|
outb(TS_DATA, 0x14);
|
|
|
|
outb(GN_MISCOUTW, (inb(GN_MISCOUTR) | 0x08)); /* Misc output register */
|
|
|
|
vsp->wd132col = 1;
|
|
}
|
|
else /* switch 132 -> 80 */
|
|
{
|
|
if(!regsaved) /* failsafe */
|
|
{
|
|
/* disable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
|
|
/* disable access to WD/Paradise "control extensions" */
|
|
|
|
outb(GDC_INDEX, GDC_PR5GPLOCK);
|
|
outb(GDC_INDEX, 0x00);
|
|
outb(addr_6845, CRTC_PR10);
|
|
outb(addr_6845, 0x00);
|
|
outb(TS_INDEX, TS_UNLOCKSEQ);
|
|
outb(TS_DATA, 0x00);
|
|
|
|
vga_screen_on();
|
|
|
|
return(0);
|
|
}
|
|
|
|
sp = savearea.wd90c11;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x2e); /* misc 1 */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x2f); /* misc 2 */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(TS_INDEX, 0x10);/* Timing Sequencer */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(TS_INDEX, 0x12);/* Timing Sequencer */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(GN_MISCOUTW, *sp++); /* Misc output register */
|
|
|
|
vsp->wd132col = 0;
|
|
}
|
|
|
|
/* restore fonts */
|
|
|
|
#if !PCVT_BACKUP_FONTS
|
|
for(i = 0; i < totalfonts; i++)
|
|
{
|
|
if(sv_fontwd[i])
|
|
vga_move_charset(i, sv_fontwd[i], 0);
|
|
}
|
|
#else
|
|
for(i = 0; i < totalfonts; i++)
|
|
if(saved_charsets[i])
|
|
vga_move_charset(i, 0, 0);
|
|
#endif /* !PCVT_BACKUP_FONTS */
|
|
|
|
select_vga_charset(vsp->vga_charset);
|
|
|
|
/* disable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
|
|
/* disable access to WD/Paradise "control extensions" */
|
|
|
|
outb(GDC_INDEX, GDC_PR5GPLOCK);
|
|
outb(GDC_INDEX, 0x00);
|
|
outb(addr_6845, CRTC_PR10);
|
|
outb(addr_6845, 0x00);
|
|
outb(TS_INDEX, TS_UNLOCKSEQ);
|
|
outb(TS_DATA, 0x00);
|
|
|
|
vga_screen_on();
|
|
|
|
return(1);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* toggle 80/132 column operation for TRIDENT 9000 based boards
|
|
*---------------------------------------------------------------------------*/
|
|
int
|
|
tri9000_col(int cols)
|
|
{
|
|
u_char *sp;
|
|
u_char byte;
|
|
|
|
vga_screen_off();
|
|
|
|
/* sync reset is necessary to preserve memory contents ... */
|
|
|
|
outb(TS_INDEX, TS_SYNCRESET);
|
|
outb(TS_DATA, 0x01); /* synchronous reset */
|
|
|
|
/* disable protection of misc out and other regs */
|
|
|
|
outb(addr_6845, CRTC_MTEST);
|
|
byte = inb(addr_6845+1);
|
|
outb(addr_6845, CRTC_MTEST);
|
|
outb(addr_6845+1, byte & ~0x50);
|
|
|
|
/* enable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
byte = inb(addr_6845+1);
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte & 0x7f);
|
|
|
|
if(cols == SCR_COL132) /* switch 80 -> 132 */
|
|
{
|
|
/* save state of board for 80 columns */
|
|
|
|
if(!regsaved)
|
|
{
|
|
regsaved = 1;
|
|
|
|
sp = savearea.tri9000;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x13);
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
outb(TS_INDEX, TS_HWVERS);/* Hardware Version register */
|
|
outb(TS_DATA, 0x00); /* write ANYTHING switches to OLD */
|
|
outb(TS_INDEX, TS_MODEC2);
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
outb(TS_INDEX, TS_HWVERS);/* Hardware Version register */
|
|
inb(TS_DATA); /* read switches to NEW */
|
|
outb(TS_INDEX, TS_MODEC2);
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
*sp++ = inb(GN_MISCOUTR); /* Misc output register */
|
|
}
|
|
|
|
/* setup chipset for 132 column operation */
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, 0x9b);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, 0x83);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, 0x84);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, 0x1e);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, 0x87);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, 0x1a);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, 0x42);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, 0x01); /* 8 dot char clock */
|
|
|
|
outb(TS_INDEX, TS_HWVERS);/* Hardware Version register */
|
|
outb(TS_DATA, 0x00); /* write ANYTHING switches to OLD */
|
|
outb(TS_INDEX, TS_MODEC2);
|
|
outb(TS_DATA, 0x00);
|
|
|
|
outb(TS_INDEX, TS_HWVERS);/* Hardware Version register */
|
|
inb(TS_DATA); /* read switches to NEW */
|
|
outb(TS_INDEX, TS_MODEC2);
|
|
outb(TS_DATA, 0x01);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS); /* ATC Mode control */
|
|
outb(ATC_DATAW, 0x08); /* Line graphics disable */
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS); /* ATC Horizontal Pixel Panning */
|
|
outb(ATC_DATAW, 0x00);
|
|
|
|
outb(GN_MISCOUTW, (inb(GN_MISCOUTR) | 0x0c)); /* Misc output register */
|
|
}
|
|
else /* switch 132 -> 80 */
|
|
{
|
|
if(!regsaved) /* failsafe */
|
|
{
|
|
/* disable access to first 7 CRTC registers */
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
|
|
outb(TS_INDEX, TS_SYNCRESET);
|
|
outb(TS_DATA, 0x03); /* clear synchronous reset */
|
|
|
|
vga_screen_on();
|
|
|
|
return(0);
|
|
}
|
|
|
|
sp = savearea.tri9000;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, *sp++);
|
|
|
|
outb(TS_INDEX, TS_HWVERS);/* Hardware Version register */
|
|
outb(TS_DATA, 0x00); /* write ANYTHING switches to OLD */
|
|
outb(TS_INDEX, TS_MODEC2);/* Timing Sequencer */
|
|
outb(TS_DATA, *sp++);
|
|
|
|
outb(TS_INDEX, TS_HWVERS);/* Hardware Version register */
|
|
inb(TS_DATA); /* read switches to NEW */
|
|
outb(TS_INDEX, TS_MODEC2);/* Timing Sequencer */
|
|
outb(TS_DATA, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
outb(GN_MISCOUTW, *sp++); /* Misc output register */
|
|
}
|
|
|
|
/* disable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
|
|
outb(TS_INDEX, TS_SYNCRESET);
|
|
outb(TS_DATA, 0x03); /* clear synchronous reset */
|
|
|
|
vga_screen_on();
|
|
|
|
return(1);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* toggle 80/132 column operation for Video7 VGA 1024i
|
|
*---------------------------------------------------------------------------*/
|
|
int
|
|
v7_1024i_col(int cols)
|
|
{
|
|
u_char *sp;
|
|
u_char byte;
|
|
u_char save__byte;
|
|
|
|
vga_screen_off();
|
|
|
|
/* enable access to first 7 CRTC registers */
|
|
|
|
/* first, enable read access to vertical retrace start/end */
|
|
outb(addr_6845, CRTC_HBLANKE);
|
|
byte = inb(addr_6845+1);
|
|
outb(addr_6845, CRTC_HBLANKE);
|
|
outb(addr_6845+1, (byte | 0x80));
|
|
|
|
/* second, enable access to protected registers */
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
save__byte = byte = inb(addr_6845+1);
|
|
byte |= 0x20; /* no irq 2 */
|
|
byte &= 0x6f; /* wr enable, clr irq flag */
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
|
|
outb(TS_INDEX, TS_EXTCNTL); /* enable extensions */
|
|
outb(TS_DATA, 0xea);
|
|
|
|
|
|
if(cols == SCR_COL132) /* switch 80 -> 132 */
|
|
{
|
|
/* save state of board for 80 columns */
|
|
|
|
if(!regsaved)
|
|
{
|
|
regsaved = 1;
|
|
|
|
sp = savearea.v7_1024i;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
outb(TS_INDEX, 0x83);
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
outb(TS_INDEX, 0xa4);
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
outb(TS_INDEX, 0xe0);
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
outb(TS_INDEX, 0xe4);
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
outb(TS_INDEX, 0xf8);
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
outb(TS_INDEX, 0xfd);
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
*sp++ = inb(GN_MISCOUTR); /* Misc output register */
|
|
}
|
|
|
|
/* setup chipset for 132 column operation */
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, 0x9c);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, 0x83);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, 0x86);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, 0x9e);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, 0x89);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, 0x1c);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, 0x42);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, 0x01); /* 8 dot char clock */
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS); /* ATC Mode control */
|
|
outb(ATC_DATAW, 0x08); /* Line graphics disable */
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS); /* ATC Horizontal Pixel Panning */
|
|
outb(ATC_DATAW, 0x00);
|
|
|
|
outb(TS_INDEX, TS_SYNCRESET);
|
|
outb(TS_DATA, 0x01); /* synchronous reset */
|
|
|
|
outb(TS_INDEX, 0x83);
|
|
outb(TS_DATA, 0xa0);
|
|
|
|
outb(TS_INDEX, 0xa4);
|
|
outb(TS_DATA, 0x1c);
|
|
|
|
outb(TS_INDEX, 0xe0);
|
|
outb(TS_DATA, 0x00);
|
|
|
|
outb(TS_INDEX, 0xe4);
|
|
outb(TS_DATA, 0xfe);
|
|
|
|
outb(TS_INDEX, 0xf8);
|
|
outb(TS_DATA, 0x1b);
|
|
|
|
outb(TS_INDEX, 0xfd);
|
|
outb(TS_DATA, 0x33);
|
|
|
|
byte = inb(GN_MISCOUTR);
|
|
byte |= 0x0c;
|
|
outb(GN_MISCOUTW, byte); /* Misc output register */
|
|
|
|
outb(TS_INDEX, TS_SYNCRESET);
|
|
outb(TS_DATA, 0x03); /* clear synchronous reset */
|
|
}
|
|
else /* switch 132 -> 80 */
|
|
{
|
|
if(!regsaved) /* failsafe */
|
|
{
|
|
outb(TS_INDEX, TS_EXTCNTL); /* disable extensions */
|
|
outb(TS_DATA, 0xae);
|
|
|
|
/* disable access to first 7 CRTC registers */
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
vga_screen_on();
|
|
return(0);
|
|
}
|
|
|
|
sp = savearea.v7_1024i;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
outb(TS_INDEX, TS_SYNCRESET);
|
|
outb(TS_DATA, 0x01); /* synchronous reset */
|
|
|
|
outb(TS_INDEX, 0x83);
|
|
outb(TS_DATA, *sp++);
|
|
|
|
outb(TS_INDEX, 0xa4);
|
|
outb(TS_DATA, *sp++);
|
|
|
|
outb(TS_INDEX, 0xe0);
|
|
outb(TS_DATA, *sp++);
|
|
|
|
outb(TS_INDEX, 0xe4);
|
|
outb(TS_DATA, *sp++);
|
|
|
|
outb(TS_INDEX, 0xf8);
|
|
outb(TS_DATA, *sp++);
|
|
|
|
outb(TS_INDEX, 0xfd);
|
|
outb(TS_DATA, *sp++);
|
|
|
|
outb(GN_MISCOUTW, *sp++); /* Misc output register */
|
|
|
|
outb(TS_INDEX, TS_SYNCRESET);
|
|
outb(TS_DATA, 0x03); /* clear synchronous reset */
|
|
}
|
|
|
|
outb(TS_INDEX, TS_EXTCNTL); /* disable extensions */
|
|
outb(TS_DATA, 0xae);
|
|
|
|
/* disable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, save__byte);
|
|
|
|
vga_screen_on();
|
|
|
|
return(1);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* toggle 80/132 column operation for S3 86C928 based boards
|
|
*---------------------------------------------------------------------------*/
|
|
int
|
|
s3_928_col(int cols)
|
|
{
|
|
u_char *sp;
|
|
u_char byte;
|
|
|
|
vga_screen_off();
|
|
|
|
outb(addr_6845, 0x38);
|
|
outb(addr_6845+1, 0x48); /* unlock registers */
|
|
outb(addr_6845, 0x39);
|
|
outb(addr_6845+1, 0xa0); /* unlock registers */
|
|
|
|
/* enable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
byte = inb(addr_6845+1);
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte & 0x7f);
|
|
|
|
if(cols == SCR_COL132) /* switch 80 -> 132 */
|
|
{
|
|
/* save state of board for 80 columns */
|
|
|
|
if(!regsaved)
|
|
{
|
|
regsaved = 1;
|
|
|
|
sp = savearea.s3_928;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x34); /* Backward Compat 3 Reg */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x3b); /* Data Xfer Exec Position */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x42); /* (Clock) Mode Control */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
*sp++ = inb(GN_MISCOUTR); /* Misc output register */
|
|
}
|
|
|
|
/* setup chipset for 132 column operation */
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, 0x9a);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, 0x83);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, 0x86);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, 0x9d);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, 0x87);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, 0x1b);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, 0x42);
|
|
|
|
outb(addr_6845, 0x34);
|
|
outb(addr_6845+1, 0x10);/* enable data xfer pos control */
|
|
outb(addr_6845, 0x3b);
|
|
outb(addr_6845+1, 0x90);/* set data xfer pos value */
|
|
|
|
outb(addr_6845, 0x42); /* (Clock) Mode Control */
|
|
outb(addr_6845+1, 0x02);/* Select 40MHz Clock */
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, 0x01); /* 8 dot char clock */
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS); /* ATC Mode control */
|
|
outb(ATC_DATAW, 0x08); /* Line graphics disable */
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS); /* ATC Horizontal Pixel Panning */
|
|
outb(ATC_DATAW, 0x00);
|
|
|
|
/* Misc output register */
|
|
|
|
outb(GN_MISCOUTW, (inb(GN_MISCOUTR) | 0x0c));
|
|
}
|
|
else /* switch 132 -> 80 */
|
|
{
|
|
if(!regsaved) /* failsafe */
|
|
{
|
|
/* disable access to first 7 CRTC registers */
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
|
|
outb(addr_6845, 0x38);
|
|
outb(addr_6845+1, 0x00); /* lock registers */
|
|
outb(addr_6845, 0x39);
|
|
outb(addr_6845+1, 0x00); /* lock registers */
|
|
|
|
vga_screen_on();
|
|
return(0);
|
|
}
|
|
|
|
sp = savearea.s3_928;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x34);
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x3b);
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x42); /* Mode control */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
outb(GN_MISCOUTW, *sp++); /* Misc output register */
|
|
}
|
|
|
|
/* disable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
|
|
outb(addr_6845, 0x38);
|
|
outb(addr_6845+1, 0x00); /* lock registers */
|
|
outb(addr_6845, 0x39);
|
|
outb(addr_6845+1, 0x00); /* lock registers */
|
|
|
|
vga_screen_on();
|
|
|
|
return(1);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* toggle 80/132 column operation for Cirrus Logic 542x based boards
|
|
*---------------------------------------------------------------------------*/
|
|
int
|
|
cl_gd542x_col(int cols)
|
|
{
|
|
u_char *sp;
|
|
u_char byte;
|
|
|
|
vga_screen_off();
|
|
|
|
/* enable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
byte = inb(addr_6845+1);
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte & 0x7f);
|
|
|
|
if(cols == SCR_COL132) /* switch 80 -> 132 */
|
|
{
|
|
/* save state of board for 80 columns */
|
|
|
|
if(!regsaved)
|
|
{
|
|
regsaved = 1;
|
|
|
|
sp = savearea.cirrus;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
*sp++ = inb(addr_6845+1);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
*sp++ = inb(addr_6845+1);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
*sp++ = inb(TS_DATA);
|
|
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
*sp++ = inb(ATC_DATAR);
|
|
|
|
*sp++ = inb(GN_MISCOUTR); /* Misc output register */
|
|
outb(addr_6845, 0x1b); /* Extended Diplay Controls */
|
|
*sp++ = inb(addr_6845+1);
|
|
}
|
|
|
|
/* setup chipset for 132 column operation */
|
|
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, 0x9f);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, 0x83);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, 0x84);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, 0x82);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, 0x8a);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, 0x9e);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, 0x42);
|
|
|
|
outb(addr_6845, 0x1b);
|
|
byte = inb(addr_6845+1);
|
|
outb(addr_6845, 0x1b);
|
|
outb(addr_6845+1, byte | (1 << 6));
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, 0x01); /* 8 dot char clock */
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS); /* ATC Mode control */
|
|
outb(ATC_DATAW, 0x08); /* Line graphics disable */
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS); /* ATC Horizontal Pixel Panning */
|
|
outb(ATC_DATAW, 0x00);
|
|
/* Misc output register */
|
|
/* use the 41.164 MHz clock */
|
|
outb(GN_MISCOUTW, (inb(GN_MISCOUTR) & ~0x0c) | (2 << 2));
|
|
}
|
|
else /* switch 132 -> 80 */
|
|
{
|
|
if(!regsaved) /* failsafe */
|
|
{
|
|
/* disable access to first 7 CRTC registers */
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
vga_screen_on();
|
|
return(0);
|
|
}
|
|
|
|
sp = savearea.generic;
|
|
|
|
outb(addr_6845, 0x00); /* Horizontal Total */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x01); /* Horizontal Display End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x02); /* Horizontal Blank Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x03); /* Horizontal Blank End */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x04); /* Horizontal Retrace Start */
|
|
outb(addr_6845+1, *sp++);
|
|
outb(addr_6845, 0x05); /* Horizontal Retrace End */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(addr_6845, 0x13); /* Row Offset Register */
|
|
outb(addr_6845+1, *sp++);
|
|
|
|
outb(TS_INDEX, TS_MODE);/* Timing Sequencer */
|
|
outb(TS_DATA, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Mode control */
|
|
outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
if(color)
|
|
inb(GN_INPSTAT1C);
|
|
else
|
|
inb(GN_INPSTAT1M);
|
|
/* ATC Horizontal Pixel Panning */
|
|
outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);
|
|
outb(ATC_DATAW, *sp++);
|
|
|
|
outb(GN_MISCOUTW, *sp++); /* Misc output register */
|
|
|
|
outb(addr_6845, 0x1b);
|
|
outb(addr_6845+1, *sp++); /* Extended Display Register */
|
|
}
|
|
|
|
/* disable access to first 7 CRTC registers */
|
|
|
|
outb(addr_6845, CRTC_VSYNCE);
|
|
outb(addr_6845+1, byte);
|
|
|
|
vga_screen_on();
|
|
|
|
return(1);
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* switch screen from text mode to X-mode and vice versa
|
|
*---------------------------------------------------------------------------*/
|
|
#if PCVT_USL_VT_COMPAT
|
|
static void
|
|
pcvt_x_hook(int tografx)
|
|
{
|
|
int i;
|
|
|
|
#if PCVT_SCREENSAVER
|
|
static unsigned saved_scrnsv_tmo = 0;
|
|
#endif /* PCVT_SCREENSAVER*/
|
|
|
|
#if PCVT_NETBSD
|
|
extern u_short *Crtat;
|
|
#endif /* PCVT_NETBSD */
|
|
|
|
/* save area for grahpics mode switch */
|
|
|
|
if(!tografx)
|
|
{
|
|
/* into standard text mode */
|
|
/* step 1: restore fonts */
|
|
for(i = 0; i < totalfonts; i++)
|
|
if(saved_charsets[i])
|
|
vga_move_charset(i, 0, 0);
|
|
|
|
|
|
#if PCVT_SCREENSAVER
|
|
/* step 2: activate screen saver */
|
|
if(saved_scrnsv_tmo)
|
|
pcvt_set_scrnsv_tmo(saved_scrnsv_tmo);
|
|
#endif /* PCVT_SCREENSAVER */
|
|
|
|
/* step 3: re-initialize lost MDA information */
|
|
if(adaptor_type == MDA_ADAPTOR)
|
|
{
|
|
/*
|
|
* Due to the fact that HGC registers are
|
|
* write-only, the Xserver can only make
|
|
* guesses about the state the HGC adaptor
|
|
* has been before turning on X mode. Thus,
|
|
* the display must be re-enabled now, and
|
|
* the cursor shape and location restored.
|
|
*/
|
|
/* enable display, text mode */
|
|
outb(GN_DMCNTLM, 0x28);
|
|
|
|
/* restore cursor mode and shape */
|
|
outb(addr_6845, CRTC_CURSORH);
|
|
outb(addr_6845+1,
|
|
((vsp->Crtat + vsp->cur_offset) - Crtat) >> 8);
|
|
outb(addr_6845, CRTC_CURSORL);
|
|
outb(addr_6845+1,
|
|
((vsp->Crtat + vsp->cur_offset) - Crtat));
|
|
|
|
outb(addr_6845, CRTC_CURSTART);
|
|
outb(addr_6845+1, vsp->cursor_start);
|
|
outb(addr_6845, CRTC_CUREND);
|
|
outb(addr_6845+1, vsp->cursor_end);
|
|
}
|
|
|
|
/* step 4: restore screen and re-enable text output */
|
|
|
|
/* kernel memory -> video board memory */
|
|
bcopyb(vsp->Memory, Crtat,
|
|
vsp->screen_rowsize * vsp->maxcol * CHR);
|
|
|
|
vsp->Crtat = Crtat; /* operate on-screen now */
|
|
|
|
outb(addr_6845, CRTC_STARTADRH);
|
|
outb(addr_6845+1, 0);
|
|
outb(addr_6845, CRTC_STARTADRL);
|
|
outb(addr_6845+1, 0);
|
|
|
|
/* step 5: make status display happy */
|
|
async_update(0);
|
|
}
|
|
else /* tografx */
|
|
{
|
|
/* switch to graphics mode: save everything we need */
|
|
|
|
/* step 1: deactivate screensaver */
|
|
|
|
#if PCVT_SCREENSAVER
|
|
if(saved_scrnsv_tmo = scrnsv_timeout)
|
|
pcvt_set_scrnsv_tmo(0); /* turn it off */
|
|
#endif /* PCVT_SCREENSAVER */
|
|
|
|
/* step 2: handle status display */
|
|
async_update(1); /* turn off */
|
|
|
|
/* step 3: disable text output and save screen contents */
|
|
|
|
/* video board memory -> kernel memory */
|
|
bcopyb(vsp->Crtat, vsp->Memory,
|
|
vsp->screen_rowsize * vsp->maxcol * CHR);
|
|
|
|
vsp->Crtat = vsp->Memory; /* operate in memory now */
|
|
}
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* switch to virtual screen n (0 ... PCVT_NSCREENS-1), VT_USL version
|
|
* (the name vgapage() stands for historical reasons)
|
|
*---------------------------------------------------------------------------*/
|
|
int
|
|
vgapage(int new_screen)
|
|
{
|
|
int x;
|
|
|
|
if(new_screen < 0 || new_screen >= totalscreens)
|
|
return EINVAL;
|
|
|
|
if(vsp->proc != pfind(vsp->pid))
|
|
/* XXX what is this for? */
|
|
vt_switch_pending = 0;
|
|
|
|
if(vt_switch_pending)
|
|
return EAGAIN;
|
|
|
|
vt_switch_pending = new_screen + 1;
|
|
|
|
x = spltty();
|
|
if(vs[new_screen].vt_status & VT_WAIT_ACT)
|
|
{
|
|
wakeup((caddr_t)&vs[new_screen].smode);
|
|
vs[new_screen].vt_status &= ~VT_WAIT_ACT;
|
|
}
|
|
splx(x);
|
|
|
|
if(new_screen == current_video_screen)
|
|
{
|
|
vt_switch_pending = 0;
|
|
return 0;
|
|
}
|
|
|
|
/* fallback to VT_AUTO if controlling processes died */
|
|
if(vsp->proc
|
|
&& vsp->proc != pfind(vsp->pid))
|
|
vsp->smode.mode = VT_AUTO;
|
|
if(vs[new_screen].proc
|
|
&& vs[new_screen].proc != pfind(vs[new_screen].pid))
|
|
vs[new_screen].smode.mode = VT_AUTO;
|
|
|
|
if(vsp->smode.mode == VT_PROCESS)
|
|
{
|
|
/* we cannot switch immediately here */
|
|
vsp->vt_status |= VT_WAIT_REL;
|
|
if(vsp->smode.relsig)
|
|
psignal(vsp->proc, vsp->smode.relsig);
|
|
}
|
|
else
|
|
{
|
|
int modechange = 0;
|
|
|
|
if((vs[new_screen].vt_status & VT_GRAFX) !=
|
|
(vsp->vt_status & VT_GRAFX))
|
|
{
|
|
if(vsp->vt_status & VT_GRAFX)
|
|
modechange = 1; /* to text */
|
|
else
|
|
modechange = 2; /* to grfx */
|
|
}
|
|
|
|
if(modechange == 2)
|
|
pcvt_x_hook(1);
|
|
|
|
switch_screen(new_screen, vsp->vt_status & VT_GRAFX);
|
|
|
|
if(modechange == 1)
|
|
pcvt_x_hook(0);
|
|
|
|
if(vsp->smode.mode == VT_PROCESS)
|
|
{
|
|
/* if _new_ vt is under process control... */
|
|
vsp->vt_status |= VT_WAIT_ACK;
|
|
if(vsp->smode.acqsig)
|
|
psignal(vsp->proc, vsp->smode.acqsig);
|
|
}
|
|
else
|
|
/* we are comitted */
|
|
vt_switch_pending = 0;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*---------------------------------------------------------------------------*
|
|
* ioctl handling for VT_USL mode
|
|
*---------------------------------------------------------------------------*/
|
|
int
|
|
usl_vt_ioctl(Dev_t dev, int cmd, caddr_t data, int flag, struct proc *p)
|
|
{
|
|
int i, j, error;
|
|
|
|
switch(cmd)
|
|
{
|
|
|
|
#if PCVT_FAKE_SYSCONS10
|
|
case CONS_GETVERS:
|
|
*(int *)data = 0x100; /* fake syscons 1.0 */
|
|
return 0;
|
|
#endif /* PCVT_FAKE_SYSCONS10 */
|
|
|
|
case VT_SETMODE:
|
|
vsp->smode = *(struct vt_mode *)data;
|
|
if(vsp->smode.mode == VT_PROCESS) {
|
|
vsp->proc = p;
|
|
vsp->pid = p->p_pid;
|
|
}
|
|
return 0;
|
|
|
|
case VT_GETMODE:
|
|
*(struct vt_mode *)data = vsp->smode;
|
|
return 0;
|
|
|
|
case VT_RELDISP:
|
|
switch(*(int *)data) {
|
|
case VT_FALSE:
|
|
/* process refuses to release screen; abort */
|
|
if(vt_switch_pending
|
|
&& vt_switch_pending - 1 == current_video_screen
|
|
&& (vsp->vt_status & VT_WAIT_REL)) {
|
|
vsp->vt_status &= ~VT_WAIT_REL;
|
|
vt_switch_pending = 0;
|
|
return 0;
|
|
}
|
|
break;
|
|
|
|
case VT_TRUE:
|
|
/* process releases its VT */
|
|
if(vt_switch_pending
|
|
&& minor(dev) == current_video_screen
|
|
&& (vsp->vt_status & VT_WAIT_REL)) {
|
|
int new_screen = vt_switch_pending - 1;
|
|
int modechange = 0;
|
|
|
|
vsp->vt_status &= ~VT_WAIT_REL;
|
|
|
|
if((vs[new_screen].vt_status & VT_GRAFX) !=
|
|
(vsp->vt_status & VT_GRAFX))
|
|
{
|
|
if(vsp->vt_status & VT_GRAFX)
|
|
modechange = 1; /* to text */
|
|
else
|
|
modechange = 2; /* to grfx */
|
|
}
|
|
|
|
if(modechange == 2)
|
|
pcvt_x_hook(1);
|
|
|
|
switch_screen(new_screen,
|
|
vsp->vt_status & VT_GRAFX);
|
|
|
|
if(modechange == 1)
|
|
pcvt_x_hook(0);
|
|
|
|
if(vsp->smode.mode == VT_PROCESS) {
|
|
/*
|
|
* if the new vt is also in process
|
|
* mode, we have to wait until its
|
|
* controlling process acknowledged
|
|
* the switch
|
|
*/
|
|
vsp->vt_status
|
|
|= VT_WAIT_ACK;
|
|
if(vsp->smode.acqsig)
|
|
psignal(vsp->proc,
|
|
vsp->smode.acqsig);
|
|
}
|
|
else
|
|
/* we are comitted */
|
|
vt_switch_pending = 0;
|
|
return 0;
|
|
}
|
|
break;
|
|
|
|
case VT_ACKACQ:
|
|
/* new vts controlling process acknowledged */
|
|
if(vsp->vt_status & VT_WAIT_ACK) {
|
|
vt_switch_pending = 0;
|
|
vsp->vt_status &= ~VT_WAIT_ACK;
|
|
return 0;
|
|
}
|
|
break;
|
|
}
|
|
return EINVAL; /* end case VT_RELDISP */
|
|
|
|
|
|
case VT_OPENQRY:
|
|
/* return free vt */
|
|
for(i = 0; i < PCVT_NSCREENS; i++)
|
|
if(!vs[i].openf) {
|
|
*(int *)data = i + 1;
|
|
return 0;
|
|
}
|
|
return EAGAIN;
|
|
|
|
case VT_GETACTIVE:
|
|
*(int *)data = current_video_screen + 1;
|
|
return 0;
|
|
|
|
case VT_ACTIVATE:
|
|
return vgapage(*(int *)data - 1);
|
|
|
|
case VT_WAITACTIVE:
|
|
/* sleep until vt switch happened */
|
|
i = *(int *)data - 1;
|
|
|
|
if(i != -1
|
|
&& (i < 0 || i >= PCVT_NSCREENS))
|
|
return EINVAL;
|
|
|
|
if(i != -1
|
|
&& minor(dev) == i)
|
|
return 0;
|
|
|
|
if(i == -1)
|
|
{
|
|
int x = spltty();
|
|
vsp->vt_status |= VT_WAIT_ACT;
|
|
while((error = tsleep((caddr_t)&vsp->smode,
|
|
PZERO | PCATCH, "waitvt", 0))
|
|
== ERESTART)
|
|
;
|
|
vsp->vt_status &= ~VT_WAIT_ACT;
|
|
splx(x);
|
|
}
|
|
else
|
|
{
|
|
int x = spltty();
|
|
vs[i].vt_status |= VT_WAIT_ACT;
|
|
while((error = tsleep((caddr_t)&vs[i].smode,
|
|
PZERO | PCATCH, "waitvt", 0))
|
|
== ERESTART)
|
|
;
|
|
vs[i].vt_status &= ~VT_WAIT_ACT;
|
|
splx(x);
|
|
}
|
|
return error;
|
|
|
|
case KDENABIO:
|
|
/* grant the process IO access; only allowed if euid == 0 */
|
|
{
|
|
|
|
#if PCVT_NETBSD || (PCVT_FREEBSD && PCVT_FREEBSD > 102)
|
|
struct trapframe *fp = (struct trapframe *)p->p_regs;
|
|
#else
|
|
struct syscframe *fp = (struct syscframe *)p->p_regs;
|
|
#endif /* PCVT_NETBSD || PCVT_FREEBSD > 102 */
|
|
|
|
if(suser(p->p_ucred, &p->p_acflag) != 0)
|
|
return (EPERM);
|
|
|
|
#if PCVT_NETBSD || (PCVT_FREEBSD && PCVT_FREEBSD > 102)
|
|
fp->tf_eflags |= PSL_IOPL;
|
|
#else
|
|
fp->sf_eflags |= PSL_IOPL;
|
|
#endif /* PCVT_NETBSD || PCVT_FREEBSD > 102 */
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
case KDDISABIO:
|
|
/* abandon IO access permission */
|
|
{
|
|
|
|
#if PCVT_NETBSD || (PCVT_FREEBSD && PCVT_FREEBSD > 102)
|
|
struct trapframe *fp = (struct trapframe *)p->p_regs;
|
|
fp->tf_eflags &= ~PSL_IOPL;
|
|
#else
|
|
struct syscframe *fp = (struct syscframe *)p->p_regs;
|
|
fp->sf_eflags &= ~PSL_IOPL;
|
|
#endif /* PCVT_NETBSD || PCVT_FREEBSD > 102 */
|
|
|
|
return 0;
|
|
}
|
|
|
|
case KDSETMODE:
|
|
{
|
|
struct video_state *vsx = &vs[minor(dev)];
|
|
int haschanged = 0;
|
|
|
|
if(adaptor_type != VGA_ADAPTOR
|
|
&& adaptor_type != MDA_ADAPTOR)
|
|
/* X will only run on those adaptors */
|
|
return (EINVAL);
|
|
|
|
/* set text/graphics mode of current vt */
|
|
switch(*(int *)data)
|
|
{
|
|
case KD_TEXT:
|
|
haschanged = (vsx->vt_status & VT_GRAFX) != 0;
|
|
vsx->vt_status &= ~VT_GRAFX;
|
|
if(haschanged && vsx == vsp)
|
|
pcvt_x_hook(0);
|
|
return 0;
|
|
|
|
case KD_GRAPHICS:
|
|
haschanged = (vsx->vt_status & VT_GRAFX) == 0;
|
|
vsx->vt_status |= VT_GRAFX;
|
|
if(haschanged && vsx == vsp)
|
|
pcvt_x_hook(1);
|
|
return 0;
|
|
|
|
}
|
|
return EINVAL; /* end case KDSETMODE */
|
|
}
|
|
|
|
case KDSETRAD:
|
|
/* set keyboard repeat and delay */
|
|
return kbdioctl(dev, KBDSTPMAT, data, flag);
|
|
|
|
case KDSKBMODE:
|
|
switch(*(int *)data)
|
|
{
|
|
case K_RAW:
|
|
|
|
#if PCVT_SCANSET == 2
|
|
/* put keyboard to return ancient PC scan codes */
|
|
kbc_8042cmd(CONTR_WRITE);
|
|
outb(CONTROLLER_DATA,
|
|
#if PCVT_USEKBDSEC /* security enabled */
|
|
(COMMAND_SYSFLG|COMMAND_IRQEN|COMMAND_PCSCAN));
|
|
#else /* no security */
|
|
(COMMAND_INHOVR|COMMAND_SYSFLG|COMMAND_IRQEN|COMMAND_PCSCAN));
|
|
#endif /* PCVT_USEKBDSEC */
|
|
#endif /* PCVT_SCANSET == 2 */
|
|
|
|
pcvt_kbd_raw = 1;
|
|
shift_down = meta_down = altgr_down = ctrl_down = 0;
|
|
return 0;
|
|
|
|
case K_XLATE:
|
|
#if PCVT_SCANSET == 2
|
|
kbc_8042cmd(CONTR_WRITE);
|
|
outb(CONTROLLER_DATA,
|
|
#if PCVT_USEKBDSEC /* security enabled */
|
|
(COMMAND_SYSFLG|COMMAND_IRQEN));
|
|
#else /* no security */
|
|
(COMMAND_INHOVR|COMMAND_SYSFLG|COMMAND_IRQEN));
|
|
#endif /* PCVT_USEKBDSEC */
|
|
#endif /* PCVT_SCANSET == 2 */
|
|
|
|
pcvt_kbd_raw = 0;
|
|
return 0;
|
|
}
|
|
return EINVAL; /* end KDSKBMODE */
|
|
|
|
case KDMKTONE:
|
|
/* ring the speaker */
|
|
if(data) {
|
|
int duration = *(int *)data >> 16;
|
|
int pitch = *(int *)data & 0xffff;
|
|
|
|
sysbeep(pitch, duration * hz / 3000);
|
|
}
|
|
else
|
|
sysbeep(PCVT_SYSBEEPF / 1493, hz / 4);
|
|
return 0;
|
|
|
|
case KDSETLED:
|
|
/* set kbd LED status */
|
|
/* unfortunately, the LED definitions between pcvt and */
|
|
/* USL differ some way :-( */
|
|
i = *(int *)data;
|
|
j = (i & LED_CAP? KBD_CAPSLOCK: 0)
|
|
+ (i & LED_NUM? KBD_NUMLOCK: 0)
|
|
+ (i & LED_SCR? KBD_SCROLLLOCK: 0);
|
|
return kbdioctl(dev, KBDSLOCK, (caddr_t)&j, flag);
|
|
|
|
case KDGETLED:
|
|
/* get kbd LED status */
|
|
if((error = kbdioctl(dev, KBDGLOCK, (caddr_t)&j, flag)))
|
|
return error;
|
|
i = (j & KBD_CAPSLOCK? LED_CAP: 0)
|
|
+ (j & KBD_NUMLOCK? LED_NUM: 0)
|
|
+ (j & KBD_SCROLLLOCK? LED_SCR: 0);
|
|
*(int *)data = i;
|
|
return 0;
|
|
|
|
case GIO_KEYMAP:
|
|
get_usl_keymap((keymap_t *)data);
|
|
return 0;
|
|
} /* end case cmd */
|
|
|
|
return -1; /* inappropriate usl_vt_compat ioctl */
|
|
}
|
|
#endif /* PCVT_USL_VT_COMPAT */
|
|
|
|
#endif /* NVT > 0 */
|
|
|
|
/* ------------------------- E O F ------------------------------------------*/
|
|
|