837 lines
25 KiB
C
837 lines
25 KiB
C
/* $NetBSD: gtpci.c,v 1.10 2003/07/14 15:47:17 lukem Exp $ */
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/*
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* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Allegro Networks, Inc., and Wasabi Systems, Inc.
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* 4. The name of Allegro Networks, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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* 5. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
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* WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: gtpci.c,v 1.10 2003/07/14 15:47:17 lukem Exp $");
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#include "opt_marvell.h"
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <lib/libkern/libkern.h>
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#define _BUS_SPACE_PRIVATE
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#define _BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciconf.h>
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#include <dev/marvell/gtreg.h>
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#include <dev/marvell/gtvar.h>
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#include <dev/marvell/gtintrreg.h>
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#include <dev/marvell/gtpcireg.h>
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#include <dev/marvell/gtpcivar.h>
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#include <dev/marvell/gtvar.h>
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static int gtpci_error_intr(void *);
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static void gtpci_bus_init(struct gtpci_chipset *);
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static void gtpci_bus_attach_hook(struct device *, struct device *,
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struct pcibus_attach_args *);
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static int gtpci_bus_maxdevs(pci_chipset_tag_t, int);
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static const char *
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gtpci_intr_string(pci_chipset_tag_t, pci_intr_handle_t);
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static const struct evcnt *
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gtpci_intr_evcnt(pci_chipset_tag_t, pci_intr_handle_t);
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static void *gtpci_intr_establish(pci_chipset_tag_t, pci_intr_handle_t,
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int, int (*)(void *), void *);
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static void gtpci_intr_disestablish(pci_chipset_tag_t, void *);
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#ifdef DEBUG
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int gtpci_debug = 0;
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#endif
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struct gtpci_softc {
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struct device gtpci_dev;
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struct gtpci_chipset gtpci_gtpc;
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};
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static int gtpci_cfprint(void *, const char *);
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static int gtpci_match(struct device *, struct cfdata *, void *);
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static void gtpci_attach(struct device *, struct device *, void *);
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CFATTACH_DECL(gtpci, sizeof(struct gtpci_softc),
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gtpci_match, gtpci_attach, NULL, NULL);
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extern struct cfdriver gtpci_cd;
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const struct pci_chipset_functions gtpci_functions = {
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gtpci_bus_attach_hook,
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gtpci_bus_maxdevs,
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gtpci_md_bus_devorder,
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gtpci_make_tag,
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gtpci_decompose_tag,
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gtpci_conf_read,
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gtpci_conf_write,
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gtpci_md_conf_hook,
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gtpci_md_conf_interrupt,
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gtpci_md_intr_map,
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gtpci_intr_string,
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gtpci_intr_evcnt,
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gtpci_intr_establish,
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gtpci_intr_disestablish
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};
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static const int pci_irqs[2][3] = {
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{ IRQ_PCI0_0, IRQ_PCI0_1, IRQ_PCI0_2 },
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{ IRQ_PCI1_0, IRQ_PCI1_1, IRQ_PCI1_2 },
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};
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static const struct pci_init {
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int bar_regno;
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u_int32_t bar_enable;
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bus_addr_t low_decode;
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bus_addr_t high_decode;
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bus_addr_t barsize;
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bus_addr_t accctl_high;
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bus_addr_t accctl_low;
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bus_addr_t accctl_top;
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} pci_initinfo[2][4] = {
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{
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{
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0x10, PCI_BARE_SCS0En,
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GT_SCS0_Low_Decode, GT_SCS0_High_Decode,
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PCI_SCS0_BAR_SIZE(0),
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PCI_ACCESS_CONTROL_BASE_HIGH(0, 0),
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PCI_ACCESS_CONTROL_BASE_LOW(0, 0),
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PCI_ACCESS_CONTROL_TOP(0, 0),
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}, {
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0x14, PCI_BARE_SCS1En,
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GT_SCS1_Low_Decode, GT_SCS1_High_Decode,
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PCI_SCS1_BAR_SIZE(0),
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PCI_ACCESS_CONTROL_BASE_HIGH(0, 1),
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PCI_ACCESS_CONTROL_BASE_LOW(0, 1),
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PCI_ACCESS_CONTROL_TOP(0, 1),
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}, {
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0x18, PCI_BARE_SCS2En,
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GT_SCS2_Low_Decode, GT_SCS2_High_Decode,
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PCI_SCS2_BAR_SIZE(0),
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PCI_ACCESS_CONTROL_BASE_HIGH(0, 2),
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PCI_ACCESS_CONTROL_BASE_LOW(0, 2),
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PCI_ACCESS_CONTROL_TOP(0, 2),
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}, {
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0x1c, PCI_BARE_SCS3En,
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GT_SCS3_Low_Decode, GT_SCS3_High_Decode,
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PCI_SCS3_BAR_SIZE(0),
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PCI_ACCESS_CONTROL_BASE_HIGH(0, 3),
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PCI_ACCESS_CONTROL_BASE_LOW(0, 3),
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PCI_ACCESS_CONTROL_TOP(0, 3),
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},
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}, {
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{
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0x10, PCI_BARE_SCS0En,
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GT_SCS0_Low_Decode, GT_SCS0_High_Decode,
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PCI_SCS0_BAR_SIZE(1),
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PCI_ACCESS_CONTROL_BASE_HIGH(1, 0),
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PCI_ACCESS_CONTROL_BASE_LOW(1, 0),
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PCI_ACCESS_CONTROL_TOP(1, 0),
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}, {
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0x14, PCI_BARE_SCS1En,
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GT_SCS1_Low_Decode, GT_SCS1_High_Decode,
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PCI_SCS1_BAR_SIZE(1),
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PCI_ACCESS_CONTROL_BASE_HIGH(1, 1),
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PCI_ACCESS_CONTROL_BASE_LOW(1, 1),
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PCI_ACCESS_CONTROL_TOP(1, 1),
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}, {
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0x18, PCI_BARE_SCS2En,
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GT_SCS2_Low_Decode, GT_SCS2_High_Decode,
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PCI_SCS2_BAR_SIZE(1),
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PCI_ACCESS_CONTROL_BASE_HIGH(1, 2),
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PCI_ACCESS_CONTROL_BASE_LOW(1, 2),
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PCI_ACCESS_CONTROL_TOP(1, 2),
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}, {
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0x1c, PCI_BARE_SCS3En,
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GT_SCS3_Low_Decode, GT_SCS3_High_Decode,
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PCI_SCS3_BAR_SIZE(1),
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PCI_ACCESS_CONTROL_BASE_HIGH(1, 3),
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PCI_ACCESS_CONTROL_BASE_LOW(1, 3),
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PCI_ACCESS_CONTROL_TOP(1, 3),
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},
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}
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};
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int
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gtpci_match(struct device *parent, struct cfdata *self, void *aux)
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{
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struct gt_softc * const gt = (struct gt_softc *) parent;
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struct gt_attach_args * const ga = aux;
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return GT_PCIOK(gt, ga, >pci_cd);
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}
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int
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gtpci_cfprint(void *aux, const char *pnp)
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{
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struct pcibus_attach_args *pba = (struct pcibus_attach_args *) aux;
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if (pnp)
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aprint_normal("pci at %s", pnp);
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aprint_normal(" bus %d", pba->pba_bus);
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return (UNCONF);
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}
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void
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gtpci_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pcibus_attach_args pba;
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struct gt_attach_args * const ga = aux;
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struct gt_softc * const gt = (struct gt_softc *) parent;
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struct gtpci_softc * const gtp = (struct gtpci_softc *) self;
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struct gtpci_chipset * const gtpc = >p->gtpci_gtpc;
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struct pci_chipset * const pc = >pc->gtpc_pc;
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const int busno = ga->ga_unit;
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uint32_t data;
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GT_PCIFOUND(gt, ga);
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pc->pc_funcs = >pci_functions;
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pc->pc_parent = self;
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gtpc->gtpc_busno = busno;
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gtpc->gtpc_cfgaddr = PCI_CONFIG_ADDR(busno);
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gtpc->gtpc_cfgdata = PCI_CONFIG_DATA(busno);
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gtpc->gtpc_syncreg = PCI_SYNC_REG(busno);
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gtpc->gtpc_gt_memt = ga->ga_memt;
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gtpc->gtpc_gt_memh = ga->ga_memh;
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/*
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* Let's find out where we are located.
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*/
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data = gtpci_read(gtpc, PCI_P2P_CONFIGURATION(gtpc->gtpc_busno));
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gtpc->gtpc_self = gtpci_make_tag(>pc->gtpc_pc,
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PCI_P2PCFG_BusNum_GET(data), PCI_P2PCFG_DevNum_GET(data), 0);
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switch (busno) {
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case 0:
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gtpc->gtpc_io_bs = gt->gt_pci0_iot;
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gtpc->gtpc_mem_bs = gt->gt_pci0_memt;
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gtpc->gtpc_host = gt->gt_pci0_host;
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break;
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case 1:
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gtpc->gtpc_io_bs = gt->gt_pci1_iot;
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gtpc->gtpc_mem_bs = gt->gt_pci1_memt;
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gtpc->gtpc_host = gt->gt_pci1_host;
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break;
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default:
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break;
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}
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/*
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* If no bus_spaces exist, then it's been disabled.
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*/
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if (gtpc->gtpc_io_bs == NULL && gtpc->gtpc_mem_bs == NULL) {
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aprint_normal(": disabled\n");
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return;
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}
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aprint_normal("\n");
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/*
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* clear any pre-existing error interrupt(s)
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* clear latched pci error registers
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* establish ISRs for PCI errors
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* enable PCI error interrupts
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*/
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gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno), 0);
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gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), 0);
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(void)gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
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(void)gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
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(void)gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
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(void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
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(void)gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
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if (gtpc->gtpc_host) {
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intr_establish(pci_irqs[gtpc->gtpc_busno][0], IST_LEVEL,
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IPL_GTERR, gtpci_error_intr, pc);
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intr_establish(pci_irqs[gtpc->gtpc_busno][1], IST_LEVEL,
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IPL_GTERR, gtpci_error_intr, pc);
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intr_establish(pci_irqs[gtpc->gtpc_busno][2], IST_LEVEL,
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IPL_GTERR, gtpci_error_intr, pc);
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aprint_normal("%s: %s%d error interrupts at irqs %s, %s, %s\n",
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pc->pc_parent->dv_xname, "pci", busno,
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intr_string(pci_irqs[gtpc->gtpc_busno][0]),
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intr_string(pci_irqs[gtpc->gtpc_busno][1]),
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intr_string(pci_irqs[gtpc->gtpc_busno][2]));
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gtpci_write(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno),
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PCI_SERRMSK_ALL_ERRS);
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}
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/*
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* Fill in the pci_bus_attach_args
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*/
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pba.pba_pc = pc;
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pba.pba_bus = 0;
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pba.pba_busname = "pci";
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pba.pba_iot = gtpc->gtpc_io_bs;
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pba.pba_memt = gtpc->gtpc_mem_bs;
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pba.pba_dmat = gt->gt_dmat;
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pba.pba_flags = 0;
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if (pba.pba_iot != NULL)
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pba.pba_flags |= PCI_FLAGS_IO_ENABLED;
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if (pba.pba_memt != NULL)
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pba.pba_flags |= PCI_FLAGS_MEM_ENABLED;
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data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
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if (data & PCI_CMD_MRdMul)
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pba.pba_flags |= PCI_FLAGS_MRM_OKAY;
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if (data & PCI_CMD_MRdLine)
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pba.pba_flags |= PCI_FLAGS_MRL_OKAY;
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pba.pba_flags |= PCI_FLAGS_MWI_OKAY;
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gt_watchdog_service();
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/*
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* Configure the pci bus.
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*/
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config_found(self, &pba, gtpci_cfprint);
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gt_watchdog_service();
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}
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void
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gtpci_bus_init(struct gtpci_chipset *gtpc)
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{
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const struct pci_init *pi;
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uint32_t data, datal, datah;
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pcireg_t pcidata;
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int i;
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/*
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* disable all BARs to start.
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*/
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gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
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0xffffffff);
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#ifndef GT_PCI0_EXT_ARBITER
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#define GT_PCI0_EXT_ARBITER 0
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#endif
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#ifndef GT_PCI1_EXT_ARBITER
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#define GT_PCI1_EXT_ARBITER 0
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#endif
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if (gtpc->gtpc_host &&
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((!GT_PCI0_EXT_ARBITER && gtpc->gtpc_busno == 0) ||
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(!GT_PCI1_EXT_ARBITER && gtpc->gtpc_busno == 1))) {
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/*
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* Enable internal arbiter
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*/
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data = gtpci_read(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno));
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data |= PCI_ARBCTL_EN;
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gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), data);
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} else {
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/*
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* Make sure the internal arbiter is disabled
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*/
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gtpci_write(gtpc, PCI_ARBITER_CONTROL(gtpc->gtpc_busno), 0);
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}
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/*
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* Make the GT reflects reality.
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* We always enable internal memory.
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*/
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if (gtpc->gtpc_host) {
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pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self,
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0x20) & 0xfff;
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gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self, 0x20,
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GT_LowAddr_GET(gtpci_read(gtpc, GT_Internal_Decode)) |
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pcidata);
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}
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data = PCI_BARE_IntMemEn;
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for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++)
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gtpci_write(gtpc, pi->barsize, 0);
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if (gtpc->gtpc_host) {
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/*
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* Enable bus master access (needed for config access).
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*/
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pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self,
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PCI_COMMAND_STATUS_REG);
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pcidata |= PCI_COMMAND_MASTER_ENABLE;
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gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self,
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PCI_COMMAND_STATUS_REG, pcidata);
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}
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/*
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* Map each SCS BAR to correspond to each SDRAM decode register.
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*/
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for (i = 0, pi = pci_initinfo[gtpc->gtpc_busno]; i < 4; i++, pi++) {
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datal = gtpci_read(gtpc, pi->low_decode);
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datah = gtpci_read(gtpc, pi->high_decode);
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pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self,
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pi->bar_regno);
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gtpci_write(gtpc, pi->accctl_high, 0);
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if (datal < datah) {
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datal &= 0xfff;
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pcidata &= 0xfff;
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pcidata |= datal << 20;
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data |= pi->bar_enable;
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datah -= datal;
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datal |= PCI_ACCCTLBASEL_PrefetchEn|
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PCI_ACCCTLBASEL_RdPrefetch|
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PCI_ACCCTLBASEL_RdLinePrefetch|
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PCI_ACCCTLBASEL_RdMulPrefetch|
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PCI_ACCCTLBASEL_WBurst_8_QW|
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PCI_ACCCTLBASEL_PCISwap_NoSwap;
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gtpci_write(gtpc, pi->accctl_low, datal);
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} else {
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pcidata &= 0xfff;
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datal = 0xfff|PCI_ACCCTLBASEL_PCISwap_NoSwap;
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datah = 0;
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}
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gtpci_write(gtpc, pi->barsize,
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datah ? ((datah << 20) | 0xff000) : 0);
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if (gtpc->gtpc_host) {
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gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self,
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pi->bar_regno, pcidata);
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}
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gtpci_write(gtpc, pi->accctl_low, datal);
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gtpci_write(gtpc, pi->accctl_top, datah);
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}
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/*
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* Now re-enable those BARs that are real.
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*/
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gtpci_write(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno),
|
|
~data);
|
|
|
|
if (gtpc->gtpc_host) {
|
|
/*
|
|
* Enable I/O and memory (bus master is already enabled) access.
|
|
*/
|
|
pcidata = gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self,
|
|
PCI_COMMAND_STATUS_REG);
|
|
pcidata |= PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE;
|
|
gtpci_conf_write(>pc->gtpc_pc, gtpc->gtpc_self,
|
|
PCI_COMMAND_STATUS_REG, pcidata);
|
|
}
|
|
}
|
|
|
|
void
|
|
gtpci_bus_attach_hook(struct device *parent, struct device *self,
|
|
struct pcibus_attach_args *pba)
|
|
{
|
|
struct gtpci_chipset *gtpc = (struct gtpci_chipset *) pba->pba_pc;
|
|
uint32_t data;
|
|
#if defined(DEBUG)
|
|
pcitag_t tag;
|
|
int bus, dev;
|
|
int i;
|
|
#endif
|
|
|
|
if (gtpc->gtpc_pc.pc_parent != parent)
|
|
return;
|
|
|
|
data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
|
|
aprint_normal(": id %d%s%s%s%s%s%s%s%s",
|
|
PCI_MODE_PciID_GET(data),
|
|
(data & PCI_MODE_Pci64) ? ", 64bit" : "",
|
|
(data & PCI_MODE_ExpRom) ? ", Expansion Rom" : "",
|
|
(data & PCI_MODE_VPD) ? ", VPD" : "",
|
|
(data & PCI_MODE_MSI) ? ", MSI" : "",
|
|
(data & PCI_MODE_PMG) ? ", PMG" : "",
|
|
(data & PCI_MODE_HotSwap) ? ", HotSwap" : "",
|
|
(data & PCI_MODE_BIST) ? ", BIST" : "",
|
|
(data & PCI_MODE_PRst) ? "" : ", PRst");
|
|
|
|
#if 0
|
|
while ((data & PCI_MODE_PRst) == 0) {
|
|
DELAY(10);
|
|
data = gtpci_read(gtpc, PCI_MODE(gtpc->gtpc_busno));
|
|
aprint_normal(".");
|
|
}
|
|
#endif
|
|
|
|
gtpci_bus_init(gtpc);
|
|
gtpci_bus_configure(gtpc);
|
|
|
|
data = gtpci_read(gtpc, PCI_COMMAND(gtpc->gtpc_busno));
|
|
if (data & (PCI_CMD_MSwapEn|PCI_CMD_SSwapEn)) {
|
|
aprint_normal("\n%s: ", self->dv_xname);
|
|
if (data & PCI_CMD_MSwapEn) {
|
|
switch (data & (PCI_CMD_MWordSwap|PCI_CMD_MByteSwap)) {
|
|
case PCI_CMD_MWordSwap:
|
|
aprint_normal(" mswap=w"); break;
|
|
case PCI_CMD_MByteSwap:
|
|
aprint_normal(" mswap=b"); break;
|
|
case PCI_CMD_MWordSwap|PCI_CMD_MByteSwap:
|
|
aprint_normal(" mswap=b+w"); break;
|
|
case 0:
|
|
aprint_normal(" mswap=none"); break;
|
|
}
|
|
}
|
|
|
|
if (data & PCI_CMD_SSwapEn) {
|
|
switch (data & (PCI_CMD_SWordSwap|PCI_CMD_SByteSwap)) {
|
|
case PCI_CMD_SWordSwap:
|
|
aprint_normal(" sswap=w"); break;
|
|
case PCI_CMD_SByteSwap:
|
|
aprint_normal(" sswap=b"); break;
|
|
case PCI_CMD_SWordSwap|PCI_CMD_SByteSwap:
|
|
aprint_normal(" sswap=b+w"); break;
|
|
case 0:
|
|
aprint_normal(" sswap=none"); break;
|
|
}
|
|
}
|
|
}
|
|
|
|
#if defined(DEBUG)
|
|
if (gtpci_debug == 0)
|
|
return;
|
|
|
|
data = gtpci_read(gtpc, PCI_BASE_ADDR_REGISTERS_ENABLE(gtpc->gtpc_busno));
|
|
aprint_normal("\n%s: BARs enabled: %#x", self->dv_xname, data);
|
|
|
|
aprint_normal("\n%s: 0:0:0\n", self->dv_xname);
|
|
aprint_normal(" %sSCS0=%#010x",
|
|
(data & 1) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x10));
|
|
aprint_normal("/%#010x", gtpci_read(gtpc,
|
|
PCI_SCS0_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x\n",
|
|
gtpci_read(gtpc, PCI_SCS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
|
|
|
|
aprint_normal(" %sSCS1=%#010x",
|
|
(data & 2) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x14));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_SCS1_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x\n",
|
|
gtpci_read(gtpc, PCI_SCS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
|
|
|
|
aprint_normal(" %sSCS2=%#010x",
|
|
(data & 4) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x18));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_SCS2_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x\n",
|
|
gtpci_read(gtpc, PCI_SCS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
|
|
|
|
aprint_normal(" %sSCS3=%#010x",
|
|
(data & 8) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x1c));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_SCS3_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x\n",
|
|
gtpci_read(gtpc, PCI_SCS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
|
|
|
|
aprint_normal(" %sIMem=%#010x",
|
|
(data & PCI_BARE_IntMemEn) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x20));
|
|
aprint_normal("\n");
|
|
aprint_normal(" %sIIO=%#010x",
|
|
(data & PCI_BARE_IntIOEn) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, gtpc->gtpc_self, 0x24));
|
|
aprint_normal("\n");
|
|
|
|
gtpci_decompose_tag(>pc->gtpc_pc, gtpc->gtpc_self, &bus, &dev, NULL);
|
|
tag = gtpci_make_tag(>pc->gtpc_pc, bus, dev, 1);
|
|
aprint_normal(" %sCS0=%#010x",
|
|
(data & PCI_BARE_CS0En) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, tag, 0x10));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_CS0_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x\n",
|
|
gtpci_read(gtpc, PCI_CS0_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
|
|
|
|
aprint_normal(" %sCS1=%#010x",
|
|
(data & PCI_BARE_CS1En) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, tag, 0x14));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_CS1_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x\n",
|
|
gtpci_read(gtpc, PCI_CS1_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
|
|
|
|
aprint_normal(" %sCS2=%#010x",
|
|
(data & PCI_BARE_CS2En) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, tag, 0x18));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_CS2_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x\n",
|
|
gtpci_read(gtpc, PCI_CS2_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
|
|
|
|
aprint_normal(" %sCS3=%#010x",
|
|
(data & PCI_BARE_CS3En) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_CS3_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x\n",
|
|
gtpci_read(gtpc, PCI_CS3_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
|
|
|
|
aprint_normal(" %sBootCS=%#010x",
|
|
(data & PCI_BARE_BootCSEn) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, tag, 0x20));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_BOOTCS_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x\n",
|
|
gtpci_read(gtpc, PCI_BOOTCS_ADDR_REMAP(gtpc->gtpc_busno)));
|
|
|
|
tag = gtpci_make_tag(>pc->gtpc_pc, bus, tag, 2);
|
|
aprint_normal(" %sP2PM0=%#010x",
|
|
(data & PCI_BARE_P2PMem0En) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, tag, 0x10));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_P2P_MEM0_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x.%#010x\n",
|
|
gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
|
|
gtpci_read(gtpc, PCI_P2P_MEM0_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
|
|
|
|
aprint_normal(" %sP2PM1=%#010x",
|
|
(data & PCI_BARE_P2PMem1En) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, tag, 0x14));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_P2P_MEM1_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x.%#010x\n",
|
|
gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_HIGH(gtpc->gtpc_busno)),
|
|
gtpci_read(gtpc, PCI_P2P_MEM1_BASE_ADDR_REMAP_LOW(gtpc->gtpc_busno)));
|
|
|
|
aprint_normal(" %sP2PIO=%#010x",
|
|
(data & PCI_BARE_P2PIOEn) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, tag, 0x18));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_P2P_IO_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x\n",
|
|
gtpci_read(gtpc, PCI_P2P_IO_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
|
|
|
|
aprint_normal(" %sCPU=%#010x",
|
|
(data & PCI_BARE_CPUEn) ? "-" : "+",
|
|
gtpci_conf_read(>pc->gtpc_pc, tag, 0x1c));
|
|
aprint_normal("/%#010x",
|
|
gtpci_read(gtpc, PCI_CPU_BAR_SIZE(gtpc->gtpc_busno)));
|
|
aprint_normal(" remap %#010x\n",
|
|
gtpci_read(gtpc, PCI_CPU_BASE_ADDR_REMAP(gtpc->gtpc_busno)));
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
aprint_normal("\n%s: Access Control %d: ", self->dv_xname, i);
|
|
data = gtpci_read(gtpc,
|
|
PCI_ACCESS_CONTROL_BASE_HIGH(gtpc->gtpc_busno, i));
|
|
if (data)
|
|
aprint_normal("base=0x%08x.", data);
|
|
else
|
|
aprint_normal("base=0x");
|
|
data = gtpci_read(gtpc,
|
|
PCI_ACCESS_CONTROL_BASE_LOW(gtpc->gtpc_busno, i));
|
|
printf("%08x cfg=0x%08x", data << 20, data & ~0xfff);
|
|
aprint_normal(" top=0x%03x00000",
|
|
gtpci_read(gtpc,
|
|
PCI_ACCESS_CONTROL_TOP(gtpc->gtpc_busno, i)));
|
|
}
|
|
#endif
|
|
}
|
|
|
|
static const char * const gtpci_error_strings[] = PCI_IC_SEL_Strings;
|
|
|
|
int
|
|
gtpci_error_intr(void *arg)
|
|
{
|
|
pci_chipset_tag_t pc = arg;
|
|
struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
|
|
uint32_t cause, mask, errmask;
|
|
u_int32_t alo, ahi, dlo, dhi, cmd;
|
|
int i;
|
|
|
|
cause = gtpci_read(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno));
|
|
errmask = gtpci_read(gtpc, PCI_ERROR_MASK(gtpc->gtpc_busno));
|
|
cause &= errmask | 0xf8000000;
|
|
gtpci_write(gtpc, PCI_ERROR_CAUSE(gtpc->gtpc_busno), ~cause);
|
|
printf("%s: pci%d error: cause=%#x mask=%#x",
|
|
pc->pc_parent->dv_xname, gtpc->gtpc_busno, cause, errmask);
|
|
if ((cause & 0xf8000000) == 0) {
|
|
printf(" ?\n");
|
|
return 0;
|
|
}
|
|
|
|
for (i = 0, mask = 1; i <= 26; i++, mask += mask)
|
|
if (mask & cause)
|
|
printf(" %s", gtpci_error_strings[i]);
|
|
|
|
/*
|
|
* "no new data is latched until the PCI Error Low Address
|
|
* register is read. This means that PCI Error Low Address
|
|
* register must be the last register read by the interrupt
|
|
* handler."
|
|
*/
|
|
dlo = gtpci_read(gtpc, PCI_ERROR_DATA_LOW(gtpc->gtpc_busno));
|
|
dhi = gtpci_read(gtpc, PCI_ERROR_DATA_HIGH(gtpc->gtpc_busno));
|
|
cmd = gtpci_read(gtpc, PCI_ERROR_COMMAND(gtpc->gtpc_busno));
|
|
ahi = gtpci_read(gtpc, PCI_ERROR_ADDRESS_HIGH(gtpc->gtpc_busno));
|
|
alo = gtpci_read(gtpc, PCI_ERROR_ADDRESS_LOW(gtpc->gtpc_busno));
|
|
printf("\n%s: pci%d error: %s cmd=%#x",
|
|
pc->pc_parent->dv_xname, gtpc->gtpc_busno,
|
|
gtpci_error_strings[PCI_IC_SEL_GET(cause)], cmd);
|
|
if (dhi == 0)
|
|
printf(" data=%08x", dlo);
|
|
else
|
|
printf(" data=%08x.%08x", dhi, dlo);
|
|
if (ahi == 0)
|
|
printf(" address=%08x\n", alo);
|
|
else
|
|
printf(" address=%08x.%08x\n", ahi, alo);
|
|
|
|
#if defined(DEBUG) && defined(DDB)
|
|
if (gtpci_debug > 1)
|
|
Debugger();
|
|
#endif
|
|
return 1;
|
|
}
|
|
|
|
|
|
#if 0
|
|
void
|
|
gtpci_bs_region_add(pci_chipset_tag_t pc, struct discovery_bus_space *bs,
|
|
struct gt_softc *gt, bus_addr_t lo, bus_addr_t hi)
|
|
{
|
|
/* See how I/O space is configured. Read the base and top
|
|
* registers.
|
|
*/
|
|
paddr_t pbasel, pbaseh;
|
|
uint32_t datal, datah;
|
|
|
|
datal = gtpci_read(gtpc, lo);
|
|
datah = gtpci_read(gtpc, hi);
|
|
pbasel = GT_LowAddr_GET(datal);
|
|
pbaseh = GT_HighAddr_GET(datah);
|
|
/*
|
|
* If the start is greater than the end, ignore the region.
|
|
*/
|
|
if (pbaseh < pbasel)
|
|
return;
|
|
if ((pbasel & gt->gt_iobat_mask) == gt->gt_iobat_pbase
|
|
&& (pbaseh & gt->gt_iobat_mask) == gt->gt_iobat_pbase) {
|
|
bs->bs_regions[bs->bs_nregion].br_vbase =
|
|
gt->gt_iobat_vbase + (pbasel & ~gt->gt_iobat_mask);
|
|
}
|
|
bs->bs_regions[bs->bs_nregion].br_pbase = pbasel;
|
|
if (bs->bs_flags & _BUS_SPACE_RELATIVE) {
|
|
bs->bs_regions[bs->bs_nregion].br_start = 0;
|
|
bs->bs_regions[bs->bs_nregion].br_end = pbaseh - pbasel;
|
|
} else {
|
|
bs->bs_regions[bs->bs_nregion].br_start = pbasel;
|
|
bs->bs_regions[bs->bs_nregion].br_end = pbaseh;
|
|
}
|
|
bs->bs_nregion++;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Internal functions.
|
|
*/
|
|
int
|
|
gtpci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
|
|
{
|
|
return 32;
|
|
}
|
|
|
|
pcitag_t
|
|
gtpci_make_tag(pci_chipset_tag_t pc, int busno, int devno, int funcno)
|
|
{
|
|
return PCI_CFG_MAKE_TAG(busno, devno, funcno, 0);
|
|
}
|
|
|
|
void
|
|
gtpci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag,
|
|
int *bp, int *dp, int *fp)
|
|
{
|
|
if (bp != NULL)
|
|
*bp = PCI_CFG_GET_BUSNO(tag);
|
|
if (dp != NULL)
|
|
*dp = PCI_CFG_GET_DEVNO(tag);
|
|
if (fp != NULL)
|
|
*fp = PCI_CFG_GET_FUNCNO(tag);
|
|
}
|
|
|
|
pcireg_t
|
|
gtpci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int regno)
|
|
{
|
|
struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
|
|
#ifdef DIAGNOSTIC
|
|
if ((regno & 3) || (regno & ~0xff))
|
|
panic("gtpci_conf_read: bad regno %#x\n", regno);
|
|
#endif
|
|
gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
|
|
return gtpci_read(gtpc, gtpc->gtpc_cfgdata);
|
|
}
|
|
|
|
void
|
|
gtpci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int regno, pcireg_t data)
|
|
{
|
|
struct gtpci_chipset *gtpc = (struct gtpci_chipset *)pc;
|
|
#ifdef DIAGNOSTIC
|
|
if ((regno & 3) || (regno & ~0xff))
|
|
panic("gtpci_conf_write: bad regno %#x\n", regno);
|
|
#endif
|
|
gtpci_write(gtpc, gtpc->gtpc_cfgaddr, (int) tag | regno);
|
|
gtpci_write(gtpc, gtpc->gtpc_cfgdata, data);
|
|
}
|
|
|
|
const char *
|
|
gtpci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t pih)
|
|
{
|
|
return intr_string(pih);
|
|
}
|
|
|
|
const struct evcnt *
|
|
gtpci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t pih)
|
|
{
|
|
return intr_evcnt(pih);
|
|
}
|
|
|
|
void *
|
|
gtpci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t pih,
|
|
int ipl, int (*handler)(void *), void *arg)
|
|
{
|
|
return intr_establish(pih, IST_LEVEL, ipl, handler, arg);
|
|
}
|
|
|
|
void
|
|
gtpci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
|
|
{
|
|
intr_disestablish(cookie);
|
|
}
|