91 lines
3.9 KiB
C
91 lines
3.9 KiB
C
/* $NetBSD: pciide_amd_reg.h,v 1.6 2003/01/24 05:51:04 thorpej Exp $ */
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/*
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* Copyright (c) 2000 David Sainty.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Registers definitions for AMD 7x6 PCI IDE controller. Documentation
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* available at:
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* http://www.amd.com/products/cpg/athlon/techdocs/pdf/22548.pdf (756)
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* http://www.amd.com/products/cpg/athlon/techdocs/pdf/23167.pdf (766)
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*/
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/* Chip revisions */
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#define AMD756_CHIPREV_D2 3
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/* Chip revision tests */
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/*
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* The AMD756 chip revision D2 has a bug affecting DMA (but not UDMA)
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* modes. The workaround documented by AMD is to not use DMA on any
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* drive which does not support UDMA modes.
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*
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* See: http://www.amd.com/products/cpg/athlon/techdocs/pdf/22591.pdf
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*/
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#define AMD756_CHIPREV_DISABLEDMA(rev) ((rev) <= AMD756_CHIPREV_D2)
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/*
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* The nVidia nForce and nForce2 IDE controllers are compatible with
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* the AMD controllers, but their registers are offset 0x10 bytes.
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*/
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#define AMD7X6_AMD_REGBASE 0x40
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#define AMD7X6_NVIDIA_REGBASE 0x50
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/* Channel enable */
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#define AMD7X6_CHANSTATUS_EN(sc) ((sc)->sc_amd_regbase + 0x00)
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#define AMD7X6_CHAN_EN(chan) (0x01 << (1 - (chan)))
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/* Data port timing controls */
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#define AMD7X6_DATATIM(sc) ((sc)->sc_amd_regbase + 0x08)
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#define AMD7X6_DATATIM_MASK(channel) (0xffff << ((1 - (channel)) << 4))
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#define AMD7X6_DATATIM_RECOV(channel, drive, x) (((x) & 0xf) << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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#define AMD7X6_DATATIM_PULSE(channel, drive, x) (((x) & 0xf) << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3) + 4))
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static const int8_t amd7x6_pio_set[] = {0x0a, 0x0a, 0x0a, 0x02, 0x02};
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static const int8_t amd7x6_pio_rec[] = {0x08, 0x08, 0x08, 0x02, 0x00};
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/* Ultra-DMA/33 control */
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#define AMD7X6_UDMA(sc) ((sc)->sc_amd_regbase + 0x10)
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#define AMD7X6_UDMA_MASK(channel) (0xffff << ((1 - (channel)) << 4))
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#define AMD7X6_UDMA_TIME(channel, drive, x) (((x) & 0x7) << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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#define AMD7X6_UDMA_EN(channel, drive) (0x40 << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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#define AMD7X6_UDMA_EN_MTH(channel, drive) (0x80 << \
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(((1 - (channel)) << 4) + ((1 - (drive)) << 3)))
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static const int8_t amd7x6_udma_tim[] __attribute__((__unused__)) =
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{0x02, 0x01, 0x00, 0x04, 0x05, 0x06, 0x07};
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