63d5234cbf
Several had: _MACHINE_ICU_H_ -> _NS32K_ICU_H_ cpu.h * Removed definition of cpu_swapout. * Added definition of cpu_wait. frame.h * added struct switchframe icu.h * tweeked ints_off param.h * More derived constants. * Alot of things taken over from i386/include/param.h. pcb.h * Removed pcb_flags (was unused) and pcb_pl. The current priority level is now stored in the switch frame by cpu_switch. pmap.h * Taken over from i386/include/pmap.h. psl.h * Add USERMODE definition trap.h * T_INTERRUPT -> T_AST types.h * Remove __FORK_BRAINDAMAGE vmparam.h * Taken over from i386/include/vmparam.h. Added definition of INTSTACK.
92 lines
3.3 KiB
C
92 lines
3.3 KiB
C
/* $NetBSD: trap.h,v 1.4 1996/02/01 00:03:38 phil Exp $ */
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/*
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* Mach Operating System
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* Copyright (c) 1992 Carnegie Mellon University
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* Copyright (c) 1992 Helsinki University of Technology
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* All Rights Reserved.
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*
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* Permission to use, copy, modify and distribute this software and its
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* documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON AND HELSINKI UNIVERSITY OF TECHNOLOGY ALLOW FREE USE
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* OF THIS SOFTWARE IN ITS "AS IS" CONDITION. CARNEGIE MELLON AND
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* HELSINKI UNIVERSITY OF TECHNOLOGY DISCLAIM ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie Mellon
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* the rights to redistribute these changes.
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*/
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/*
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* File: ns532/trap.h
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* Author: Tatu Ylonen, Helsinki University of Technology 1992.
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* Modified for NetBSD by Phil Nelson
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* Hardware trap vectors for ns532.
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*/
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#ifndef _MACHINE_TRAP_H_
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#define _MACHINE_TRAP_H_
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#define T_NVI 0 /* non-vectored interrupt */
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#define T_NMI 1 /* non-maskable interrupt */
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#define T_ABT 2 /* abort */
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#define T_SLAVE 3 /* coprocessor trap */
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#define T_ILL 4 /* illegal operation in user mode */
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#define T_SVC 5 /* supervisor call */
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#define T_DVZ 6 /* divide by zero */
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#define T_FLG 7 /* flag instruction */
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#define T_BPT 8 /* breakpoint instruction */
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#define T_TRC 9 /* trace trap */
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#define T_UND 10 /* undefined instruction */
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#define T_RBE 11 /* restartable bus error */
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#define T_NBE 12 /* non-restartable bus error */
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#define T_OVF 13 /* integer overflow trap */
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#define T_DBG 14 /* debug trap */
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#define T_RESERVED 15 /* reserved */
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/* Not a real trap. */
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#define T_WATCHPOINT 17 /* watchpoint */
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/* To allow for preemption */
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#define T_AST 18 /* asynchronous system trap */
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/* To include system/user mode in the trap information. */
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#define T_USER 32
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#define PARRDU_PHYS 0x28000040 /* Read parity error */
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#define PARCLU_PHYS 0x28000050 /* Clear parity error */
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#define PARRDU_VM 0xFFC80040 /* Read parity error */
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#define PARCLU_VM 0xFFC80050 /* Clear parity error */
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/* memory management status register bits and meanings. */
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#define MSR_STT 0xf0 /* CPU status. */
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#define STT_SEQ_INS 0x80 /* Sequential instruction fetch */
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#define STT_NSQ_INS 0x90 /* Non-sequential instruction fetch */
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#define STT_DATA 0xa0 /* Data transfer */
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#define STT_RMW 0xb0 /* Read/modify/write */
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#define STT_REA 0xc0 /* Read for effective address */
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#define MSR_UST 0x08 /* User/supervisor */
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#define UST_USER 0x08 /* User mode is 1. Super = 0 */
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#define MSR_DDT 0x04 /* Data Direction */
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#define DDT_WRITE 0x04 /* Write is 1. Read is 0 */
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#define MSR_TEX 0x03 /* Exception kind. */
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#define TEX_PTE1 0x01 /* First level PTE invalid */
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#define TEX_PTE2 0x02 /* Second level PTE invalid */
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#define TEX_PROT 0x03 /* Protection violation */
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#endif
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