425 lines
11 KiB
C
425 lines
11 KiB
C
/* $NetBSD: int.c,v 1.9 2004/07/08 10:10:49 sekiya Exp $ */
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/*
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* Copyright (c) 2004 Christopher SEKIYA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* INT/INT2/INT3 interrupt controller (used in Indy's, Indigo's, etc..)
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: int.c,v 1.9 2004/07/08 10:10:49 sekiya Exp $");
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#include "opt_cputype.h"
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <dev/ic/i8253reg.h>
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#include <machine/sysconf.h>
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#include <machine/machtype.h>
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#include <machine/bus.h>
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#include <mips/locore.h>
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#include <mips/cache.h>
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#include <sgimips/dev/int2reg.h>
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#include <sgimips/dev/int2var.h>
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static bus_space_handle_t ioh;
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static bus_space_tag_t iot;
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struct int_softc {
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struct device sc_dev;
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};
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static int int_match(struct device *, struct cfdata *, void *);
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static void int_attach(struct device *, struct device *, void *);
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void int_local0_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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void int_local1_intr(u_int32_t, u_int32_t, u_int32_t, u_int32_t);
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int int_mappable_intr(void *);
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void *int_intr_establish(int, int, int (*)(void *), void *);
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unsigned long int_cal_timer(void);
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void int_8254_cal(void);
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CFATTACH_DECL(int, sizeof(struct int_softc),
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int_match, int_attach, NULL, NULL);
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static int
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int_match(struct device *parent, struct cfdata *match, void *aux)
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{
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if ((mach_type == MACH_SGI_IP12) || (mach_type == MACH_SGI_IP20) ||
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(mach_type == MACH_SGI_IP22) )
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return 1;
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return 0;
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}
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static void
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int_attach(struct device *parent, struct device *self, void *aux)
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{
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u_int32_t address;
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if (mach_type == MACH_SGI_IP12)
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address = INT_IP12;
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else if (mach_type == MACH_SGI_IP20)
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address = INT_IP20;
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else if (mach_type == MACH_SGI_IP22) {
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if (mach_subtype == MACH_SGI_IP22_FULLHOUSE)
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address = INT_IP22;
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else
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address = INT_IP24;
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} else
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panic("\nint0: passed match, but failed attach?");
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printf(" addr 0x%x", address);
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bus_space_map(iot, address, 0, 0, &ioh);
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iot = SGIMIPS_BUS_SPACE_NORMAL;
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/* Clean out interrupt masks */
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bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, 0);
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bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, 0);
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bus_space_write_4(iot, ioh, INT2_MAP_MASK0, 0);
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bus_space_write_4(iot, ioh, INT2_MAP_MASK1, 0);
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/* Reset timer interrupts */
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bus_space_write_4(iot, ioh, INT2_TIMER_CLEAR, 0x03);
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switch (mach_type) {
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case MACH_SGI_IP12:
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platform.intr1 = int_local0_intr;
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platform.intr2 = int_local1_intr;
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int_8254_cal();
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break;
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#ifdef MIPS3
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case MACH_SGI_IP20:
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case MACH_SGI_IP22:
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{
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int i;
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unsigned long cps;
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unsigned long ctrdiff[3];
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platform.intr0 = int_local0_intr;
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platform.intr1 = int_local1_intr;
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/* calibrate timer */
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int_cal_timer();
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cps = 0;
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for (i = 0;
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i < sizeof(ctrdiff) / sizeof(ctrdiff[0]); i++) {
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do {
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ctrdiff[i] = int_cal_timer();
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} while (ctrdiff[i] == 0);
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cps += ctrdiff[i];
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}
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cps = cps / (sizeof(ctrdiff) / sizeof(ctrdiff[0]));
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printf(": bus %luMHz, CPU %luMHz",
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cps / 10000, cps / 5000);
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/* R4k/R4400/R4600/R5k count at half CPU frequency */
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curcpu()->ci_cpu_freq = 2 * cps * hz;
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}
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#endif /* MIPS3 */
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break;
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default:
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panic("int0: unsupported machine type %i\n", mach_type);
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break;
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}
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printf("\n");
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curcpu()->ci_cycles_per_hz = curcpu()->ci_cpu_freq / (2 * hz);
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curcpu()->ci_divisor_delay = curcpu()->ci_cpu_freq / (2 * 1000000);
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MIPS_SET_CI_RECIPRICAL(curcpu());
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if (mach_type == MACH_SGI_IP22) {
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/* Wire interrupts 7, 11 to mappable interrupt 0,1 handlers */
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intrtab[7].ih_fun = int_mappable_intr;
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intrtab[7].ih_arg = (void*) 0;
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intrtab[11].ih_fun = int_mappable_intr;
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intrtab[11].ih_arg = (void*) 1;
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}
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platform.intr_establish = int_intr_establish;
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}
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int
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int_mappable_intr(void *arg)
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{
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int i;
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int ret;
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int intnum;
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u_int32_t mstat;
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u_int32_t mmask;
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int which = (int)arg;
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struct sgimips_intrhand *ih;
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ret = 0;
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mstat = bus_space_read_4(iot, ioh, INT2_MAP_STATUS);
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mmask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0 + (which << 2));
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mstat &= mmask;
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for (i = 0; i < 8; i++) {
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intnum = i + 16 + (which << 3);
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if (mstat & (1 << i)) {
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for (ih = &intrtab[intnum]; ih != NULL;
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ih = ih->ih_next) {
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if (ih->ih_fun != NULL)
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ret |= (ih->ih_fun)(ih->ih_arg);
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else
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printf("int0: unexpected mapped "
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"interrupt %d\n", intnum);
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}
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}
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}
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return ret;
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}
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void
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int_local0_intr(u_int32_t status, u_int32_t cause, u_int32_t pc,
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u_int32_t ipending)
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{
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int i;
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u_int32_t l0stat;
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u_int32_t l0mask;
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struct sgimips_intrhand *ih;
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l0stat = bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS);
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l0mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK);
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/* The "FIFO full" bit is apparently not latched in the ISR, which
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means that it won't be present in l0stat unless we're very lucky.
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If no interrupts are pending, assume that it was caused by a full
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FIFO and dispatch.
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*/
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bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, l0mask & (0xfe));
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if ( (l0mask & 0x01) && ((l0stat & l0mask) == 0) )
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l0stat = 0x01;
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for (i = 0; i < 8; i++) {
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if ( (l0stat & l0mask) & (1 << i)) {
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for (ih = &intrtab[i]; ih != NULL; ih = ih->ih_next) {
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if (ih->ih_fun != NULL)
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(ih->ih_fun)(ih->ih_arg);
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else
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printf("int0: unexpected local0 "
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"interrupt %d\n", i);
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}
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}
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}
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/* Unmask FIFO */
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bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, l0mask | 0x01);
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}
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void
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int_local1_intr(u_int32_t status, u_int32_t cause, u_int32_t pc,
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u_int32_t ipending)
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{
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int i;
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u_int32_t l1stat;
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u_int32_t l1mask;
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struct sgimips_intrhand *ih;
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l1stat = bus_space_read_4(iot, ioh, INT2_LOCAL1_STATUS);
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l1mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK);
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l1stat &= l1mask;
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for (i = 0; i < 8; i++) {
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if (l1stat & (1 << i)) {
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for (ih = &intrtab[8+i]; ih != NULL; ih = ih->ih_next) {
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if (ih->ih_fun != NULL)
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(ih->ih_fun)(ih->ih_arg);
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else
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printf("int0: unexpected local1 "
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" interrupt %x\n", 8 + i);
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}
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}
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}
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}
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void *
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int_intr_establish(int level, int ipl, int (*handler) (void *), void *arg)
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{
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u_int32_t mask;
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if (level < 0 || level >= NINTR)
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panic("invalid interrupt level");
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if (intrtab[level].ih_fun == NULL) {
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intrtab[level].ih_fun = handler;
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intrtab[level].ih_arg = arg;
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intrtab[level].ih_next = NULL;
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} else {
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struct sgimips_intrhand *n, *ih = malloc(sizeof *ih,
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M_DEVBUF, M_NOWAIT);
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if (ih == NULL) {
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printf("int_intr_establish: can't allocate handler\n");
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return (void *)NULL;
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}
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ih->ih_fun = handler;
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ih->ih_arg = arg;
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ih->ih_next = NULL;
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for (n = &intrtab[level]; n->ih_next != NULL; n = n->ih_next)
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;
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n->ih_next = ih;
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return (void *)NULL; /* vector already set */
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}
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if (level < 8) {
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mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK);
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mask |= (1 << level);
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bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask);
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} else if (level < 16) {
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mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK);
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mask |= (1 << (level - 8));
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bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask);
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} else if (level < 24) {
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/* Map0 interrupt maps to l0 bit 7, so turn that on too */
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mask = bus_space_read_4(iot, ioh, INT2_LOCAL0_MASK);
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mask |= (1 << 7);
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bus_space_write_4(iot, ioh, INT2_LOCAL0_MASK, mask);
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mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK0);
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mask |= (1 << (level - 16));
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bus_space_write_4(iot, ioh, INT2_MAP_MASK0, mask);
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} else {
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/* Map1 interrupt maps to l1 bit 3, so turn that on too */
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mask = bus_space_read_4(iot, ioh, INT2_LOCAL1_MASK);
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mask |= (1 << 3);
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bus_space_write_4(iot, ioh, INT2_LOCAL1_MASK, mask);
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mask = bus_space_read_4(iot, ioh, INT2_MAP_MASK1);
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mask |= (1 << (level - 24));
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bus_space_write_4(iot, ioh, INT2_MAP_MASK1, mask);
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}
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return (void *)NULL;
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}
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#ifdef MIPS3
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unsigned long
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int_cal_timer(void)
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{
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int s;
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int roundtime;
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int sampletime;
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int startmsb, lsb, msb;
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unsigned long startctr, endctr;
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/*
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* NOTE: HZ must be greater than 15 for this to work, as otherwise
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* we'll overflow the counter. We round the answer to hearest 1
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* MHz of the master (2x) clock.
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*/
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roundtime = (1000000 / hz) / 2;
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sampletime = (1000000 / hz) + 0xff;
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startmsb = (sampletime >> 8);
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s = splhigh();
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bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL,
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( TIMER_SEL2 | TIMER_16BIT | TIMER_RATEGEN) );
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bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime & 0xff));
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bus_space_write_4(iot, ioh, INT2_TIMER_2, (sampletime >> 8));
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startctr = mips3_cp0_count_read();
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/* Wait for the MSB to count down to zero */
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do {
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bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL, TIMER_SEL2 );
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lsb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff;
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msb = bus_space_read_4(iot, ioh, INT2_TIMER_2) & 0xff;
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endctr = mips3_cp0_count_read();
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} while (msb);
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/* Turn off timer */
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bus_space_write_4(iot, ioh, INT2_TIMER_CONTROL,
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( TIMER_SEL2 | TIMER_16BIT | TIMER_SWSTROBE) );
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splx(s);
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return (endctr - startctr) / roundtime * roundtime;
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}
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#endif /* MIPS3 */
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void
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int_8254_cal(void)
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{
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int s;
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s = splhigh();
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bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15,
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TIMER_SEL0|TIMER_RATEGEN|TIMER_16BIT);
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bus_space_write_1(iot, ioh, INT2_TIMER_0 + 3, (20000 / hz) % 256);
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wbflush();
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delay(4);
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bus_space_write_1(iot, ioh, INT2_TIMER_0 + 3, (20000 / hz) / 256);
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bus_space_write_1(iot, ioh, INT2_TIMER_0 + 15,
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TIMER_SEL2|TIMER_RATEGEN|TIMER_16BIT);
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bus_space_write_1(iot, ioh, INT2_TIMER_0 + 11, 50);
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wbflush();
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delay(4);
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bus_space_write_1(iot, ioh, INT2_TIMER_0 + 11, 0);
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splx(s);
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}
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void
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int2_wait_fifo(u_int32_t flag)
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{
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if (ioh == 0)
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delay(5000);
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else
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while (bus_space_read_4(iot, ioh, INT2_LOCAL0_STATUS) & flag)
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;
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}
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