ee6cde04ff
but add a second argument to it to indicate whether the TLB/caches need to be flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field to see if the fixed can be skipped. Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1) or enabeld (bit = 0). With these changes, the A9 MMU can use traverse caches to do MMU tablewalks Also, make sure all memory has the shareable bit for the A9. |
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.. | ||
g42xxeb_kmkbd.c | ||
g42xxeb_lcd.c | ||
g42xxeb_machdep.c | ||
g42xxeb_mci.c | ||
g42xxeb_reg.h | ||
g42xxeb_start.S | ||
g42xxeb_var.h | ||
gb225_pcic.c | ||
gb225_slhci.c | ||
gb225.c | ||
gb225reg.h | ||
gb225var.h | ||
if_ne_obio.c | ||
obio.c |