103 lines
3.6 KiB
C
103 lines
3.6 KiB
C
/* $NetBSD: ifpgamem.h,v 1.1 2001/10/27 16:19:09 rearnsha Exp $ */
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/*
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* Copyright (c) 2001 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Physical memory map provided by the integrator FPGA
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*/
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#define IFPGA_SDRAM_BASE 0x00000000
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#define IFPGA_SDRAM_SIZE 0x10000000 /* 256 MB */
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#define IFPGA_SSRAM_BASE 0x00000000 /* Overlaps SDRAM */
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#define IFPGA_SSRAM_SIZE 0x00040000 /* 256 KB */
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#define IFPGA_IO_BASE 0x10000000
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#define IFPGA_IO_SIZE 0x10000000 /* 256 KB */
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#define IFPGA_IO_CM_BASE 0x00000000 /* Core module regs */
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#define IFPGA_IO_CM_SIZE 0x00000200
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#define IFPGA_IO_SC_BASE 0x01000000 /* System Ctrl regs */
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#define IFPGA_IO_SC_SIZE 0x00000028
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#define IFPGA_IO_TMR_BASE 0x03000000 /* Countr/timr regs */
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#define IFPGA_IO_TMR_SIZE 0x00000210
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#define IFPGA_IO_IRQ_BASE 0x04000000 /* IRQ controller */
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#define IFPGA_IO_IRQ_SIZE 0x00000100
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#define IFPGA_TIMER0_BASE 0x00000000
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#define IFPGA_TIMER1_BASE 0x00000100
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#define IFPGA_TIMER2_BASE 0x00000200
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#define IFPGA_TIMER0_IRQ 5
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#define IFPGA_TIMER1_IRQ 6
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#define IFPGA_TIMER2_IRQ 7
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#define IFPGA_TIMER1_FREQ 24000000 /* 24 MHz */
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#define IFPGA_TIMER2_FREQ 24000000 /* 24 MHz */
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#define IFPGA_EBI_ROM_BASE 0x20000000
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#define IFPGA_EBI_ROM_SIZE 0x04000000 /* 64MB */
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#define IFPGA_EBI_FLASH_BASE 0x24000000
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#define IFPGA_EBI_FLASH_SIZE 0x04000000 /* 64MB */
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#define IFPGA_EBI_SSRAM_BASE 0x28000000
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#define IFPGA_EBI_SSRAM_SIZE 0x04000000 /* 64MB */
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#define IFPGA_PCI_BASE 0x40000000 /* Base of entire PCI
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subsystem. */
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#define IFPGA_PCI_APP0_BASE 0x40000000
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#define IFPGA_PCI_APP0_SIZE 0x10000000 /* 256MB */
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#define IFPGA_PCI_APP1_BASE 0x50000000
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#define IFPGA_PCI_APP1_SIZE 0x10000000 /* 256MB */
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#define IFPGA_PCI_IO_BASE 0x60000000 /* Absolute */
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#define IFPGA_PCI_IO_VBASE 0xfe000000
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#define IFPGA_PCI_IO_VSIZE 0x01000000 /* 16MB */
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#define IFPGA_PCI_CONF_BASE 0x61000000 /* Absolute */
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#define IFPGA_PCI_CONF_VBASE 0xff000000
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#define IFPGA_PCI_CONF_VSIZE 0x01000000 /* 16MB */
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#define IFPGA_V360_REG_BASE 0x62000000
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#define IFPGA_V360_REG_SIZE 0x00010000 /* 64K */
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/* Core module alias memory. */
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#define IFPGA_CM_ALIAS_BASE 0x80000000
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/* Logic module memory. */
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#define IFPGA_LM_BASE 0xc0000000
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