d8e5466776
- Define EISA board register set and some other magic numbers. - Add missing elements to `struct cac_controller_info'.
200 lines
6.8 KiB
C
200 lines
6.8 KiB
C
/* $NetBSD: cacreg.h,v 1.4 2000/09/01 12:10:21 ad Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Andrew Doran.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 1999 Jonathan Lemon
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _IC_CACREG_H_
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#define _IC_CACREG_H_
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/* Board register offsets */
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#define CAC_REG_CMD_FIFO 0x04
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#define CAC_REG_DONE_FIFO 0x08
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#define CAC_REG_INTR_MASK 0x0C
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#define CAC_REG_STATUS 0x10
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#define CAC_REG_INTR_PENDING 0x14
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#define CAC_42REG_CMD_FIFO 0x40
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#define CAC_42REG_DONE_FIFO 0x44
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#define CAC_42REG_INTR_MASK 0x34
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#define CAC_42REG_STATUS 0x30
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#define CAC_42REG_INTR_PENDING 0x08
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#define CAC_EISAREG_INTR_MASK 0x01
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#define CAC_EISAREG_LOCAL_MASK 0x04
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#define CAC_EISAREG_LOCAL_DOORBELL 0x05
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#define CAC_EISAREG_SYSTEM_MASK 0x06
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#define CAC_EISAREG_SYSTEM_DOORBELL 0x07
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#define CAC_EISAREG_LIST_ADDR 0x08
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#define CAC_EISAREG_LIST_LEN 0x0c
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#define CAC_EISAREG_TAG 0x0f
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#define CAC_EISAREG_COMPLETE_ADDR 0x10
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#define CAC_EISAREG_LIST_STATUS 0x16
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/* EISA channel control */
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#define CAC_EISA_CHANNEL_BUSY 0x01
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#define CAC_EISA_CHANNEL_CLEAR 0x02
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/* Interrupt mask values */
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#define CAC_INTR_DISABLE 0x00
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#define CAC_INTR_ENABLE 0x01
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/* Command types */
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#define CAC_CMD_GET_LOG_DRV_INFO 0x10
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#define CAC_CMD_GET_CTRL_INFO 0x11
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#define CAC_CMD_SENSE_DRV_STATUS 0x12
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#define CAC_CMD_START_RECOVERY 0x13
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#define CAC_CMD_GET_PHYS_DRV_INFO 0x15
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#define CAC_CMD_BLINK_DRV_LEDS 0x16
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#define CAC_CMD_SENSE_DRV_LEDS 0x17
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#define CAC_CMD_GET_LOG_DRV_EXT 0x18
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#define CAC_CMD_GET_CTRL_INFO 0x11
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#define CAC_CMD_READ 0x20
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#define CAC_CMD_WRITE 0x30
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#define CAC_CMD_WRITE_MEDIA 0x31
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#define CAC_CMD_GET_CONFIG 0x50
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#define CAC_CMD_SET_CONFIG 0x51
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#define CAC_CMD_START_FIRMWARE 0x99
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#define CAC_CMD_FLUSH_CACHE 0xc2
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/* Return status codes */
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#define CAC_RET_SOFT_ERROR 0x02
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#define CAC_RET_HARD_ERROR 0x04
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#define CAC_RET_CMD_REJECTED 0x14
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struct cac_drive_info {
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u_int16_t secsize;
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u_int32_t secperunit;
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u_int16_t ncylinders;
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u_int8_t nheads;
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u_int8_t signature;
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u_int8_t psectors;
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u_int16_t wprecomp;
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u_int8_t max_acc;
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u_int8_t control;
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u_int16_t pcylinders;
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u_int8_t ptracks;
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u_int16_t landing_zone;
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u_int8_t nsectors;
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u_int8_t checksum;
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u_int8_t mirror;
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} __attribute__((__packed__));
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struct cac_controller_info {
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u_int8_t num_drvs;
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u_int32_t signature;
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u_int8_t firm_rev[4];
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u_int8_t rom_rev[4];
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u_int8_t hw_rev;
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u_int32_t bb_rev;
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u_int32_t drv_present_map;
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u_int32_t ext_drv_map;
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u_int32_t board_id;
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u_int8_t cfg_error;
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u_int32_t non_disk_bits;
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u_int8_t bad_ram_addr;
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u_int8_t cpu_rev;
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u_int8_t pdpi_rev;
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u_int8_t epic_rev;
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u_int8_t wcxc_rev;
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u_int8_t marketing_rev;
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u_int8_t ctlr_flags;
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u_int8_t host_flags;
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u_int8_t expand_dis;
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u_int8_t scsi_chips;
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u_int32_t max_req_blocks;
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u_int32_t ctlr_clock;
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u_int8_t drvs_per_bus;
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u_int16_t big_drv_present_map[8];
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u_int16_t big_ext_drv_map[8];
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u_int16_t big_non_disk_map[8];
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u_int16_t task_flags;
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u_int8_t icl_bus;
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u_int8_t red_modes;
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u_int8_t cur_red_mode;
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u_int8_t red_ctlr_stat;
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u_int8_t red_fail_reason;
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u_int8_t reserved[403];
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} __attribute__((__packed__));
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struct cac_hdr {
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u_int8_t drive; /* logical drive */
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u_int8_t priority; /* block priority */
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u_int16_t size; /* size of request, in words */
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} __attribute__((__packed__));
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struct cac_req {
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u_int16_t next; /* offset of next request */
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u_int8_t command; /* command */
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u_int8_t error; /* return error code */
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u_int32_t blkno; /* block number */
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u_int16_t bcount; /* block count */
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u_int8_t sgcount; /* number of scatter/gather entries */
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u_int8_t reserved; /* reserved */
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} __attribute__((__packed__));
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struct cac_sgb {
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u_int32_t length; /* length of S/G segment */
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u_int32_t addr; /* physical address of block */
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} __attribute__((__packed__));
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#endif /* !_IC_CACREG_H_ */
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