165 lines
5.7 KiB
C
165 lines
5.7 KiB
C
/*
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Van Jacobson of Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)scsivar.h 7.1 (Berkeley) 5/8/90
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* $Id: sbicvar.h,v 1.2 1994/06/14 00:59:03 chopps Exp $
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*/
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#ifndef _SBICVAR_H_
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#define _SBICVAR_H_
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/*
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* The largest single request will be MAXPHYS bytes which will require
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* at most MAXPHYS/NBPG+1 chain elements to describe, i.e. if none of
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* the buffer pages are physically contiguous (MAXPHYS/NBPG) and the
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* buffer is not page aligned (+1).
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*/
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#define DMAMAXIO (MAXPHYS/NBPG+1)
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struct dma_chain {
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int dc_count;
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char *dc_addr;
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};
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struct sbic_pending {
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TAILQ_ENTRY(sbic_pending) link;
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struct scsi_xfer *xs;
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};
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struct sbic_softc {
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struct device sc_dev;
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struct target_sync {
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u_char state;
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u_char period;
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u_char offset;
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} sc_sync[8];
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struct scsi_link sc_link; /* proto for sub devices */
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sbic_regmap_p sc_sbicp; /* the SBIC */
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volatile void *sc_cregs; /* driver specific regs */
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TAILQ_HEAD(,sbic_pending) sc_xslist; /* LIFO */
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struct sbic_pending sc_xsstore[8][8]; /* one for every unit */
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struct scsi_xfer *sc_xs; /* transfer from high level code */
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u_char sc_flags;
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u_char sc_scsiaddr;
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u_char sc_stat[2];
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u_char sc_msg[7];
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u_long sc_clkfreq;
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u_long sc_tcnt; /* number of bytes transfered */
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u_char *sc_dmabuffer;
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u_char *sc_dmausrbuf;
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u_long sc_dmausrlen;
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u_short sc_dmacmd; /* used by dma drivers */
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u_short sc_dmatimo; /* dma timeout */
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u_long sc_dmamask; /* dma valid mem mask */
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struct dma_chain sc_chain[DMAMAXIO];
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struct dma_chain *sc_cur;
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struct dma_chain *sc_last;
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int (*sc_dmago) __P((struct sbic_softc *, char *, int, int));
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int (*sc_dmanext) __P((struct sbic_softc *));
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void (*sc_dmafree) __P((struct sbic_softc *));
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void (*sc_dmastop) __P((struct sbic_softc *));
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u_short gtsc_bankmask; /* GVP specific bank selected */
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};
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/* sc_flags */
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#define SBICF_ALIVE 0x01 /* controller initialized */
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#define SBICF_DCFLUSH 0x02 /* need flush for overlap after dma finishes */
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#define SBICF_SELECTED 0x04 /* bus is in selected state. */
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#define SBICF_BADDMA 0x10 /* controller can only DMA to ztwobus space */
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#define SBICF_BBUF 0x20 /* DMA input needs to be copied from bounce */
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#define SBICF_INTR 0x40 /* SBICF interrupt expected */
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#define SBICF_INDMA 0x80 /* not used yet, DMA I/O in progress */
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/* sync states */
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#define SYNC_START 0 /* no sync handshake started */
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#define SYNC_SENT 1 /* we sent sync request, no answer yet */
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#define SYNC_DONE 2 /* target accepted our (or inferior) settings,
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or it rejected the request and we stay async */
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#ifdef DEBUG
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#define DDB_FOLLOW 0x04
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#define DDB_IO 0x08
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#endif
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extern int sbic_inhibit_sync;
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extern int sbic_no_dma;
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extern int sbic_clock_override;
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#define PHASE 0x07 /* mask for psns/pctl phase */
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#define DATA_OUT_PHASE 0x00
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#define DATA_IN_PHASE 0x01
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#define CMD_PHASE 0x02
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#define STATUS_PHASE 0x03
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#define BUS_FREE_PHASE 0x04
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#define ARB_SEL_PHASE 0x05 /* Fuji chip combines arbitration with sel. */
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#define MESG_OUT_PHASE 0x06
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#define MESG_IN_PHASE 0x07
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#define MSG_CMD_COMPLETE 0x00
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#define MSG_EXT_MESSAGE 0x01
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#define MSG_SAVE_DATA_PTR 0x02
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#define MSG_RESTORE_PTR 0x03
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#define MSG_DISCONNECT 0x04
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#define MSG_INIT_DETECT_ERROR 0x05
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#define MSG_ABORT 0x06
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#define MSG_REJECT 0x07
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#define MSG_NOOP 0x08
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#define MSG_PARITY_ERROR 0x09
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#define MSG_BUS_DEVICE_RESET 0x0C
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#define MSG_IDENTIFY 0x80
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#define MSG_IDENTIFY_DR 0xc0 /* (disconnect/reconnect allowed) */
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#define MSG_SYNC_REQ 0x01
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#define STS_CHECKCOND 0x02 /* Check Condition (ie., read sense) */
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#define STS_CONDMET 0x04 /* Condition Met (ie., search worked) */
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#define STS_BUSY 0x08
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#define STS_INTERMED 0x10 /* Intermediate status sent */
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#define STS_EXT 0x80 /* Extended status valid */
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/*
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* XXXX
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*/
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struct scsi_fmt_cdb {
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int len; /* cdb length (in bytes) */
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u_char cdb[28]; /* cdb to use on next read/write */
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};
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struct buf;
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struct scsi_xfer;
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void sbic_minphys __P((struct buf *bp));
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u_int sbic_adinfo __P((void));
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int sbic_scsicmd __P((struct scsi_xfer *));
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#endif /* _SBICVAR_H_ */
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