267 lines
7.6 KiB
C
267 lines
7.6 KiB
C
/* $NetBSD: locore.h,v 1.50 2000/10/09 07:33:31 nisimura Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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* Junior University. All Rights Reserved.
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*
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. Stanford University
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*/
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/*
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* Jump table for MIPS cpu locore functions that are implemented
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* differently on different generations, or instruction-level
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* archtecture (ISA) level, the Mips family.
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* The following functions must be provided for each mips ISA level:
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*
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*
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* MachFlushCache
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* MachFlushDCache
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* MachFlushICache
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* wbflush
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* proc_trampoline()
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* cpu_switch_resume()
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*
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* We currently provide support for MIPS I and MIPS III.
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*/
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#ifndef _MIPS_LOCORE_H
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#define _MIPS_LOCORE_H
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#ifndef _LKM
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#include "opt_cputype.h"
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#include "opt_mips_cache.h"
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#endif
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struct tlb;
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/*
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* locore service routine for exception vectors. Used outside locore
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* only to print them by name in stack tracebacks
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*/
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u_int32_t mips_cp0_cause_read(void);
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void mips_cp0_cause_write(u_int32_t);
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u_int32_t mips_cp0_status_read(void);
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void mips_cp0_status_write(u_int32_t);
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int mips1_icsize(void);
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int mips1_dcsize(void);
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void mips1_FlushCache(void);
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void mips1_FlushDCache(vaddr_t addr, vsize_t len);
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void mips1_FlushICache(vaddr_t addr, vsize_t len);
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void mips1_SetPID(int pid);
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void mips1_TBIA(int);
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void mips1_TBIAP(int);
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void mips1_TBIS(vaddr_t);
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int mips1_TLBUpdate(u_int, u_int);
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void mips1_wbflush(void);
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void mips1_proc_trampoline(void);
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void mips1_cpu_switch_resume(void);
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void mips3_ConfigCache(int);
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void mips3_FlushCache(void);
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void mips3_FlushDCache(vaddr_t addr, vaddr_t len);
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void mips3_FlushICache(vaddr_t addr, vaddr_t len);
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void mips3_HitFlushDCache(vaddr_t, int);
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void mips3_SetPID(int pid);
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void mips3_TBIA(int);
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void mips3_TBIAP(int);
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void mips3_TBIS(vaddr_t);
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int mips3_TLBUpdate(u_int, u_int);
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void mips3_TLBRead(int, struct tlb *);
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void mips3_wbflush(void);
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void mips3_proc_trampoline(void);
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void mips3_cpu_switch_resume(void);
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void mips3_FlushCache_2way(void);
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void mips3_FlushDCache_2way(vaddr_t addr, vaddr_t len);
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void mips3_HitFlushDCache_2way(vaddr_t, int);
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void mips3_FlushICache_2way(vaddr_t addr, vaddr_t len);
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u_int32_t mips3_cp0_compare_read(void);
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void mips3_cp0_compare_write(u_int32_t);
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u_int32_t mips3_cp0_config_read(void);
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void mips3_cp0_count_write(u_int32_t);
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u_int32_t mips3_cp0_count_read(void);
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void mips3_cp0_config_write(u_int32_t);
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u_int32_t mips3_cp0_wired_read(void);
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void mips3_cp0_wired_write(u_int32_t);
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u_int64_t mips3_ld(u_int64_t *);
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void mips3_sd(u_int64_t *, u_int64_t);
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/*
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* A vector with an entry for each mips-ISA-level dependent
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* locore function, and macros which jump through it.
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* XXX the macro names are chosen to be compatible with the old
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* Sprite coding-convention names used in 4.4bsd/pmax.
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*/
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typedef struct {
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void (*flushCache)(void);
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void (*flushDCache)(vaddr_t addr, vsize_t len);
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void (*flushICache)(vaddr_t addr, vsize_t len);
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void (*setTLBpid)(int pid);
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void (*TBIAP)(int);
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void (*TBIS)(vaddr_t);
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int (*tlbUpdate)(u_int highreg, u_int lowreg);
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void (*wbflush)(void);
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} mips_locore_jumpvec_t;
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/* Override writebuffer-drain method. */
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void mips_set_wbflush(void (*)(void));
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/* stacktrace() -- print a stack backtrace to the console */
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void stacktrace(void);
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/* logstacktrace() -- log a stack traceback to msgbuf */
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void logstacktrace(void);
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/*
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* The "active" locore-fuction vector, and
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*/
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extern mips_locore_jumpvec_t mips_locore_jumpvec;
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extern mips_locore_jumpvec_t r2000_locore_vec;
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extern mips_locore_jumpvec_t r4000_locore_vec;
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extern long *mips_locoresw[];
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#if defined(MIPS3) && !defined (MIPS1)
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#if defined(MIPS3_5200)
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#define MachFlushCache mips3_FlushCache_2way
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#define MachFlushDCache mips3_FlushDCache_2way
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#define MachHitFlushDCache mips3_HitFlushDCache_2way
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#define MachFlushICache mips3_FlushICache_2way
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#else
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#define MachFlushCache mips3_FlushCache
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#if defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_4100)
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#define MachFlushDCache mips3_FlushDCache /* VR4100 */
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#elif !defined(MIPS3_L2CACHE_ABSENT) && defined(MIPS3_L2CACHE_PRESENT)
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#define MachFlushDCache mips3_FlushDCache
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#else
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#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache))
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#endif
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#define MachHitFlushDCache mips3_HitFlushDCache
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#define MachFlushICache mips3_FlushICache
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#endif
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#define MachSetPID mips3_SetPID
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#define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips3_TBIS
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#define MachTLBUpdate mips3_TLBUpdate
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#define wbflush() mips3_wbflush()
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#define proc_trampoline mips3_proc_trampoline
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#endif
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#if !defined(MIPS3) && defined (MIPS1)
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#define MachFlushCache mips1_FlushCache
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#define MachFlushDCache mips1_FlushDCache
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#define MachFlushICache mips1_FlushICache
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#define MachSetPID mips1_SetPID
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#define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips1_TBIS
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#define MachTLBUpdate mips1_TLBUpdate
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#define wbflush() mips1_wbflush()
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#define proc_trampoline mips1_proc_trampoline
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#endif
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#if defined(MIPS3) && defined (MIPS1)
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#define MachFlushCache (*(mips_locore_jumpvec.flushCache))
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#define MachFlushDCache (*(mips_locore_jumpvec.flushDCache))
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#define MachFlushICache (*(mips_locore_jumpvec.flushICache))
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#define MachSetPID (*(mips_locore_jumpvec.setTLBpid))
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#define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries)
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#define MIPS_TBIS (*(mips_locore_jumpvec.TBIS))
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#define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate))
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#define MachHitFlushDCache mips3_HitFlushDCache
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#define wbflush() (*(mips_locore_jumpvec.wbflush))()
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#define proc_trampoline (mips_locoresw[1])
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#endif
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#define CPU_IDLE (mips_locoresw[2])
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/* cpu_switch_resume is called inside locore.S */
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/*
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* CPU identification, from PRID register.
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*/
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typedef int mips_prid_t;
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#define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff)
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#define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff)
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/* pre-MIPS32 */
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#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff)
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#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f)
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#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f)
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/* MIPS32 */
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#define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */
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#define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32 */
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#define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */
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#ifdef _KERNEL
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/*
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* Global variables used to communicate CPU type, and parameters
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* such as cache size, from locore to higher-level code (e.g., pmap).
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*/
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extern mips_prid_t cpu_id;
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extern mips_prid_t fpu_id;
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extern int mips_num_tlb_entries;
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extern u_int mips_L1DCacheSize;
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extern u_int mips_L1ICacheSize;
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extern u_int mips_L1DCacheLSize;
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extern u_int mips_L1ICacheLSize;
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extern int mips_L2CachePresent;
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extern u_int mips_L2CacheLSize;
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extern u_int mips_CacheAliasMask;
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extern u_int mips_CachePreferMask;
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#ifdef MIPS3
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extern int mips3_L1TwoWayCache;
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extern int mips3_cacheflush_bug;
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#endif /* MIPS3 */
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/*
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* trapframe argument passed to trap()
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*/
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struct trapframe {
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mips_reg_t tf_regs[17];
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mips_reg_t tf_ra;
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mips_reg_t tf_sr;
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mips_reg_t tf_mullo;
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mips_reg_t tf_mulhi;
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mips_reg_t tf_epc; /* may be changed by trap() call */
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};
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/*
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* Stack frame for kernel traps. four args passed in registers.
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* A trapframe is pointed to by the 5th arg, and a dummy sixth argument
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* is used to avoid alignment problems
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*/
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struct kernframe {
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register_t cf_args[4 + 1];
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register_t cf_pad; /* (for 8 word alignment) */
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register_t cf_sp;
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register_t cf_ra;
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struct trapframe cf_frame;
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};
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#endif
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#endif /* _MIPS_LOCORE_H */
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