71 lines
3.5 KiB
C
71 lines
3.5 KiB
C
/*
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: dmareg.h,v 1.3 1994/10/02 22:00:17 deraadt Exp $
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*/
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struct dma_regs {
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volatile u_long csr; /* DMA CSR */
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#define D_INT_PEND 0x00000001 /* interrupt pending */
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#define D_ERR_PEND 0x00000002 /* error pending */
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#define D_DRAINING 0x0000000c /* fifo draining */
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#define D_INT_EN 0x00000010 /* interrupt enable */
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#define D_INVALIDATE 0x00000020 /* invalidate fifo */
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#define D_SLAVE_ERR 0x00000040 /* slave access size error */
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#define D_DRAIN 0x00000040 /* drain fifo if DMAREV_1 */
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#define D_RESET 0x00000080 /* reset scsi */
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#define D_WRITE 0x00000100 /* 1 = dev -> mem */
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#define D_EN_DMA 0x00000200 /* enable DMA requests */
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#define D_R_PEND 0x00000400 /* something only on ver < 2 */
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#define D_EN_CNT 0x00002000 /* enable byte counter */
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#define D_TC 0x00004000 /* terminal count */
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#define D_DSBL_CSR_DRN 0x00010000 /* disable fifo drain on csr */
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#define D_DSBL_SCSI_DRN 0x00020000 /* disable fifo drain on reg */
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#define D_BURST_SIZE 0x000c0000 /* sbus read/write burst size */
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#define D_DIAG 0x00100000 /* disable fifo drain on addr */
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#define D_TWO_CYCLE 0x00200000 /* 2 clocks per transfer */
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#define D_FASTER 0x00400000 /* 3 clocks per transfer */
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#define D_TCI_DIS 0x00800000 /* disable intr on D_TC */
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#define D_EN_NEXT 0x01000000 /* enable auto next address */
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#define D_DMA_ON 0x02000000 /* enable dma from scsi */
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#define D_A_LOADED 0x04000000 /* address loaded */
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#define D_NA_LOADED 0x08000000 /* next address loaded */
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#define D_DEV_ID 0xf0000000 /* device ID */
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#define DMAREV_0 0x00000000 /* Sunray DMA */
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#define DMAREV_1 0x80000000 /* 'DMA' */
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#define DMAREV_PLUS 0x90000000 /* 'DMA+' */
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#define DMAREV_2 0xa0000000 /* 'DMA2' */
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volatile u_long addr;
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#define DMA_D_ADDR 0x01 /* DMA ADDR (in u_longs) */
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volatile u_long bcnt; /* DMA COUNT (in u_longs) */
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#define D_BCNT_MASK 0x00ffffff /* only 24 bits */
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volatile u_long test; /* DMA TEST (in u_longs) */
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};
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