131 lines
3.3 KiB
ArmAsm
131 lines
3.3 KiB
ArmAsm
/* $NetBSD: ip22_cache.S,v 1.3 2002/03/13 13:12:29 simonb Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Code to manipulate the L2 SysAD cache on some (R4600/R5000-based)
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* SGI IP-22 (Indy) systems.
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*/
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#include <mips/asm.h>
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#include <mips/cpuregs.h>
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.set noreorder
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.set mips3
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#define PROLOGUE \
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mfc0 t0, MIPS_COP_0_STATUS ; \
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nop ; \
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nop ; \
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nop ; \
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li v0, ~MIPS_SR_INT_IE /* ints off */ ; \
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and t1, v0, t0 ; \
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or t1, MIPS3_SR_KX /* enable 64-bit */ ; \
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mtc0 t1, MIPS_COP_0_STATUS ; \
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nop ; \
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nop ; \
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nop ; \
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nop
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#define EPILOGUE \
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mtc0 t0, MIPS_COP_0_STATUS ; \
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nop ; \
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nop ; \
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nop ; \
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nop
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/*
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* ip22_sdcache_do_wbinv:
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*
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* Write-back and invalidate the cache lines [a0..a1].
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*/
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LEAF_NOPROFILE(ip22_sdcache_do_wbinv)
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PROLOGUE
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/*
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* Translate the cache indices into the magic cache
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* flush space.
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*/
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dli v0, 0x9000000080000000 /* base of cache flush space */
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or a0, v0 /* first */
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or a1, v0 /* last */
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/*
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* Flush the cache by performing a store into the
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* magic cache flush space.
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*/
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1: sw zero, 0(a0)
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bne a0, a1, 1b
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daddu a0, 32
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EPILOGUE
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j ra
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nop
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END(ip22_sdcache_do_wbinv)
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LEAF_NOPROFILE(ip22_sdcache_enable)
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PROLOGUE
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li a0, 0x1
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dsll a0, 31
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lui a1, 0x9000
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dsll32 a1, 0
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or a0, a1, a0
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sb zero, 0(a0)
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EPILOGUE
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j ra
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nop
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END(ip22_sdcache_enable)
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LEAF_NOPROFILE(ip22_sdcache_disable)
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PROLOGUE
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li a0, 0x1
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dsll a0, 31
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lui a1, 0x9000
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dsll32 a1, 0
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or a0, a1, a0
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sh zero, 0(a0)
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EPILOGUE
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j ra
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nop
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END(ip22_sdcache_disable)
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