214 lines
7.8 KiB
C
214 lines
7.8 KiB
C
/* $NetBSD: mvsocreg.h,v 1.13 2017/01/07 16:19:28 kiyohara Exp $ */
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/*
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* Copyright (c) 2007, 2008 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MVSOCREG_H_
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#define _MVSOCREG_H_
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#define MVSOC_UNITID_MASK 0xf
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#define MVSOC_UNITID_DDR 0x0 /* DDR registers */
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#define MVSOC_UNITID_DEVBUS 0x1 /* Device Bus registers */
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#define MVSOC_UNITID_MLMB 0x2 /* Mbus-L to Mbus Bridge reg */
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#define MVSOC_UNITID_PEX 0x4 /* PCI Express Interface reg */
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#define MVSOC_INTERREGS_SIZE 0x00100000 /* 1 MB */
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/*
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* Physical address of integrated peripherals
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*/
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#define UNITID2PHYS(uid) ((MVSOC_UNITID_ ## uid) << 16)
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/*
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* DDR SDRAM Controller Registers
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*/
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#define MVSOC_DDR_BASE (UNITID2PHYS(DDR)) /* 0x00000 */
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/* DDR SDRAM Contriller Address Decode Registers */
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#define MVSOC_DSC_BASE 0x01500 /* DDR SDRAM Ctrl Addr Reg */
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#define MVSOC_DSC_NCS 4
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#define MVSOC_DSC_CSBAR(x) ((x) * 8)
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#define MVSOC_DSC_CSBAR_BASE_MASK 0xff000000
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#define MVSOC_DSC_CSSR(x) ((x) * 8 + 4)
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#define MVSOC_DSC_CSSR_WINEN 0x00000001
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#define MVSOC_DSC_CSSR_SIZE_MASK 0xff000000
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/*
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* Device Bus
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*/
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#define MVSOC_DEVBUS_BASE (UNITID2PHYS(DEVBUS)) /* 0x10000 */
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/*
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* General Purpose Port Registers
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*/
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#define MVSOC_GPP_BASE (MVSOC_DEVBUS_BASE + 0x0100)
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/*
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* Two-Wire Serial Interface Registers
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*/
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#define MVSOC_TWSI_BASE (MVSOC_DEVBUS_BASE + 0x1000)
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/*
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* UART Interface Registers
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*/
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/* NS16550 compatible */
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#define MVSOC_COM0_BASE (MVSOC_DEVBUS_BASE + 0x2000)
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#define MVSOC_COM1_BASE (MVSOC_DEVBUS_BASE + 0x2100)
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/*
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* Mbus-L to Mbus Bridge Registers
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*/
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#define MVSOC_MLMB_BASE (UNITID2PHYS(MLMB)) /* 0x20000 */
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/* CPU Address Map Registers */
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#define MVSOC_MLMB_WCR(w) ((w) < 8 ? ((w) << 4) + 0x0 :\
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(((w) - 8) << 3) + 0x90)
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#define MVSOC_MLMB_WCR_WINEN (1 << 0)
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#define MVSOC_MLMB_WCR_SYNC (1 << 1) /* sync barrier */
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#define MVSOC_MLMB_WCR_TARGET(t) (((t) & 0xf) << 4)
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#define MVSOC_MLMB_WCR_GET_TARGET(reg) (((reg) >> 4) & 0xf)
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#define MVSOC_MLMB_WCR_ATTR(a) (((a) & 0xff) << 8)
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#define MVSOC_MLMB_WCR_GET_ATTR(reg) (((reg) >> 8) & 0xff)
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#define MVSOC_MLMB_WCR_SIZE_MASK 0xffff0000
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#define MVSOC_MLMB_WCR_SIZE(s) (((s) - 1) & MVSOC_MLMB_WCR_SIZE_MASK)
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#define MVSOC_MLMB_WCR_GET_SIZE(reg) \
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(((reg) & MVSOC_MLMB_WCR_SIZE_MASK) + (1 << 16))
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#define MVSOC_MLMB_WBR(w) ((w) < 8 ? ((w) << 4) + 0x4 :\
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(((w) - 8) << 3) + 0x94)
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#define MVSOC_MLMB_WBR_BASE_MASK 0xffff0000
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#define MVSOC_MLMB_WBR_GET_BASE(reg) (reg & MVSOC_MLMB_WBR_BASE_MASK)
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#define MVSOC_MLMB_WRLR(w) (((w) << 4) + 0x8)
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#define MVSOC_MLMB_WRLR_REMAP_MASK 0xffff0000
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#define MVSOC_MLMB_WRLR_GET_REMAP(reg) \
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(reg & MVSOC_MLMB_WRLR_REMAP_MASK)
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#define MVSOC_MLMB_WRHR(w) (((w) << 4) + 0xc)
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#define MVSOC_MLMB_IRBAR 0x080 /* Internal regs Base Address */
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#define MVSOC_MLMB_IRBAR_BASE_MASK 0xfff00000
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/* CPU Control and Status Registers */
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#define MVSOC_MLMB_CPUCR 0x100 /* CPU Configuration Register */
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#define MVSOC_MLMB_CPUCSR 0x104 /* CPU Control/Status Register*/
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#define MVSOC_MLMB_RSTOUTNMASKR 0x108 /* RSTOUTn Mask Register */
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#define MVSOC_MLMB_RSTOUTNMASKR_SOFTRSTOUTEN (1 << 2)
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#define MVSOC_MLMB_RSTOUTNMASKR_WDRSTOUTEN (1 << 1)
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#define MVSOC_MLMB_RSTOUTNMASKR_PEXRSTOUTEN (1 << 0)
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#define MVSOC_MLMB_SSRR 0x10c /* System Soft Reset Register */
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#define MVSOC_MLMB_SSRR_SYSTEMSOFTRST (1 << 0)
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#define MVSOC_MLMB_MLMBICR 0x110 /*Mb-L to Mb Bridge Intr Cause*/
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#define MVSOC_MLMB_MLMBIMR 0x114 /*Mb-L to Mb Bridge Intr Mask */
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#define MVSOC_MLMB_CLKGATING 0x11c /* Clock Gating Control */
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#define MVSOC_MLMB_CLKGATING_LNR (1 << 13) /* Load New Ratio */
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#define MVSOC_MLMB_CLKGATING_GPH (1 << 12) /* Go To Power Half */
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#define MVSOC_MLMB_CLKGATING_GPS (1 << 11) /* Go To Power Save */
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#define MVSOC_MLMB_CLKGATING_CR (1 << 10) /* Production Realignment */
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#define MVSOC_MLMB_CLKGATING_BIT(n) (1 << (n))
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#define MVSOC_MLMB_L2CFG 0x128 /* L2 Cache Config */
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#define MVSOC_MLMB_NWIN 4
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#define MVSOC_MLMB_WINBAR(w) (((w) << 3) + 0x180)
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#define MVSOC_MLMB_WINBAR_BASE_MASK 0xff000000
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#define MVSOC_MLMB_WINCR(w) (((w) << 3) + 0x184)
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#define MVSOC_MLMB_WINCR_EN (1 << 0)
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#define MVSOC_MLMB_WINCR_WINCS(x) (((x) & 0x1c) >> 2)
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#define MVSOC_MLMB_WINCR_SIZE_MASK 0xff000000
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/* Coherent Fabric(CFU) Control and Status */
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#define MVSOC_MLMB_CFU_FAB_CTRL 0x200
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#define MVSOC_MLMB_CFU_FAB_CTRL_PROP_ERR (0x1 << 8)
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#define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU0 (0x1 << 24)
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#define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU1 (0x1 << 25)
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#define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU2 (0x1 << 26)
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#define MVSOC_MLMB_CFU_FAB_CTRL_SNOOP_CPU3 (0x1 << 27)
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/* Coherent Fabiric Configuration */
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#define MVSOC_MLMB_CFU_FAB_CFG 0x204
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/* CFU IO Event Affinity */
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#define MVSOC_MLMB_CFU_EVA 0x208
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/* CFU IO Snoop Affinity */
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#define MVSOC_MLMB_CFU_IOA 0x20c
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/* CFU Configuration XXX: changed in ARMADA 370 */
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#define MVSOC_MLMB_CFU_CFG 0x228
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#define MVSOC_MLMB_CFU_CFG_L2_NOTIFY (0x1 << 16)
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/* CIB registers offsets */
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#define MVSOC_MLMB_CIB_CTRL_CFG 0x280
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#define MVSOC_MLMB_CIB_CTRL_CFG_WB_EN (0x1 << 0)
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#define MVSOC_MLMB_CIB_CTRL_CFG_STOP (0x1 << 9)
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#define MVSOC_MLMB_CIB_CTRL_CFG_IGN_SHARE (0x2 << 10)
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#define MVSOC_MLMB_CIB_CTRL_CFG_EMPTY (0x1 << 13)
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/* CIB barrier register */
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#define MVSOC_MLMB_CIB_BARRIER(cpu) (0x1810 + 0x100 * (cpu))
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#define MVSOC_MLMB_CIB_BARRIER_TRIGGER (0x1 << 0)
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#define MVSOC_TMR_BASE (MVSOC_MLMB_BASE + 0x0300)
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/* CPU Doorbell Registers */
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#define MVSOC_MLMB_H2CDR 0x400 /* Host-to-CPU Doorbell */
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#define MVSOC_MLMB_H2CDMR 0x404 /* Host-to-CPU Doorbell Mask */
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#define MVSOC_MLMB_C2HDR 0x408 /* CPU-to-Host Doorbell */
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#define MVSOC_MLMB_C2HDMR 0x40c /* CPU-to-Host Doorbell Mask */
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/* Local to System Bridge Interrupt {Cause,Mask} Register bits */
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#define MVSOC_MLMB_MLMBI_CPUSELFINT 0
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#define MVSOC_MLMB_MLMBI_CPUTIMER0INTREQ 1
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#define MVSOC_MLMB_MLMBI_CPUTIMER1INTREQ 2
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#define MVSOC_MLMB_MLMBI_CPUWDTIMERINTREQ 3
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#define MVSOC_MLMB_MLMBI_ACCESSERR 4
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#define MVSOC_MLMB_MLMBI_BIT64ERR 5
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#define MVSOC_MLMB_MLMBI_CPUTIMER2INTREQ 6
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#define MVSOC_MLMB_MLMBI_CPUTIMER3INTREQ 7
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#define MVSOC_MLMB_MLMBI_NIRQ 8
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/*
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* PCI-Express Interface Registers
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*/
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#define MVSOC_PEX_BASE (UNITID2PHYS(PEX)) /* 0x40000 */
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/*
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* AXI's DDR Controller Registers
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* used by Dove only ???
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*/
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/* DDR SDRAM Contriller Address Decode Registers */
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#define MVSOC_AXI_NCS 2
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#define MVSOC_AXI_MMAP1(cs) (((cs) << 4) + 0x100)
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#define MVSOC_AXI_MMAP1_STARTADDRESS(v) ((v) & 0xff800000)
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#define MVSOC_AXI_MMAP1_AREALENGTH(v) (0x10000 << (((v) & 0xf0000) >> 16))
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#define MVSOC_AXI_MMAP1_ADDRESSMASK (0x1ff << 7)
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#define MVSOC_AXI_MMAP1_VALID (1 << 0)
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#endif /* _MVSOCREG_H_ */
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