484 lines
13 KiB
C
484 lines
13 KiB
C
/* $NetBSD: mesongxl_pinctrl.c,v 1.1 2019/04/19 19:07:56 jmcneill Exp $ */
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/*-
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* Copyright (c) 2019 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mesongxl_pinctrl.c,v 1.1 2019/04/19 19:07:56 jmcneill Exp $");
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#include <sys/param.h>
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#include <arm/amlogic/meson_pinctrl.h>
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/* CBUS pinmux registers */
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#define CBUS_REG(n) ((n) << 2)
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#define REG0 CBUS_REG(0)
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#define REG1 CBUS_REG(1)
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#define REG2 CBUS_REG(2)
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#define REG3 CBUS_REG(3)
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#define REG4 CBUS_REG(4)
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#define REG5 CBUS_REG(5)
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#define REG6 CBUS_REG(6)
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#define REG7 CBUS_REG(7)
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#define REG8 CBUS_REG(8)
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#define REG9 CBUS_REG(9)
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/* AO pinmux registers */
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#define AOREG0 0x00
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#define AOREG1 0x04
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/*
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* GPIO banks. The values must match those in dt-bindings/gpio/meson-gxl-gpio.h
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*/
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enum {
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GPIOZ_0 = 0,
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GPIOZ_1,
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GPIOZ_2,
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GPIOZ_3,
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GPIOZ_4,
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GPIOZ_5,
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GPIOZ_6,
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GPIOZ_7,
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GPIOZ_8,
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GPIOZ_9,
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GPIOZ_10,
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GPIOZ_11,
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GPIOZ_12,
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GPIOZ_13,
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GPIOZ_14,
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GPIOZ_15,
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GPIOH_0 = 16,
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GPIOH_1,
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GPIOH_2,
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GPIOH_3,
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GPIOH_4,
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GPIOH_5,
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GPIOH_6,
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GPIOH_7,
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GPIOH_8,
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GPIOH_9,
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BOOT_0 = 26,
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BOOT_1,
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BOOT_2,
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BOOT_3,
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BOOT_4,
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BOOT_5,
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BOOT_6,
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BOOT_7,
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BOOT_8,
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BOOT_9,
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BOOT_10,
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BOOT_11,
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BOOT_12,
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BOOT_13,
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BOOT_14,
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BOOT_15,
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CARD_0 = 42,
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CARD_1,
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CARD_2,
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CARD_3,
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CARD_4,
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CARD_5,
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CARD_6,
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GPIODV_0 = 49,
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GPIODV_1,
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GPIODV_2,
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GPIODV_3,
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GPIODV_4,
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GPIODV_5,
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GPIODV_6,
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GPIODV_7,
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GPIODV_8,
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GPIODV_9,
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GPIODV_10,
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GPIODV_11,
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GPIODV_12,
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GPIODV_13,
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GPIODV_14,
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GPIODV_15,
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GPIODV_16,
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GPIODV_17,
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GPIODV_18,
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GPIODV_19,
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GPIODV_20,
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GPIODV_21,
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GPIODV_22,
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GPIODV_23,
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GPIODV_24,
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GPIODV_25,
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GPIODV_26,
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GPIODV_27,
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GPIODV_28,
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GPIODV_29,
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GPIOX_0 = 79,
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GPIOX_1,
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GPIOX_2,
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GPIOX_3,
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GPIOX_4,
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GPIOX_5,
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GPIOX_6,
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GPIOX_7,
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GPIOX_8,
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GPIOX_9,
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GPIOX_10,
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GPIOX_11,
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GPIOX_12,
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GPIOX_13,
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GPIOX_14,
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GPIOX_15,
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GPIOX_16,
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GPIOX_17,
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GPIOX_18,
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GPIOCLK_0 = 98,
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GPIOCLK_1,
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GPIOAO_0 = 0,
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GPIOAO_1,
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GPIOAO_2,
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GPIOAO_3,
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GPIOAO_4,
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GPIOAO_5,
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GPIOAO_6,
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GPIOAO_7,
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GPIOAO_8,
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GPIOAO_9,
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GPIO_TEST_N,
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};
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#define CBUS_GPIO(_id, _off, _bit) \
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[_id] = { \
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.id = (_id), \
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.name = __STRING(_id), \
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.oen = { \
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.type = MESON_PINCTRL_REGTYPE_GPIO, \
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.reg = CBUS_REG((_off) * 3 + 0), \
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.mask = __BIT(_bit) \
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}, \
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.out = { \
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.type = MESON_PINCTRL_REGTYPE_GPIO, \
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.reg = CBUS_REG((_off) * 3 + 1), \
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.mask = __BIT(_bit) \
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}, \
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.in = { \
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.type = MESON_PINCTRL_REGTYPE_GPIO, \
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.reg = CBUS_REG((_off) * 3 + 2), \
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.mask = __BIT(_bit) \
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}, \
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.pupden = { \
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.type = MESON_PINCTRL_REGTYPE_PULL_ENABLE, \
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.reg = CBUS_REG(_off), \
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.mask = __BIT(_bit) \
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}, \
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.pupd = { \
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.type = MESON_PINCTRL_REGTYPE_PULL, \
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.reg = CBUS_REG(_off), \
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.mask = __BIT(_bit) \
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}, \
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}
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static const struct meson_pinctrl_gpio mesongxl_periphs_gpios[] = {
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/* GPIODV */
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CBUS_GPIO(GPIODV_24, 0, 24),
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CBUS_GPIO(GPIODV_25, 0, 25),
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CBUS_GPIO(GPIODV_26, 0, 26),
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CBUS_GPIO(GPIODV_27, 0, 27),
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CBUS_GPIO(GPIODV_28, 0, 28),
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CBUS_GPIO(GPIODV_29, 0, 29),
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/* GPIOH */
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CBUS_GPIO(GPIOH_0, 1, 20),
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CBUS_GPIO(GPIOH_1, 1, 21),
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CBUS_GPIO(GPIOH_2, 1, 22),
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CBUS_GPIO(GPIOH_3, 1, 23),
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CBUS_GPIO(GPIOH_4, 1, 24),
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CBUS_GPIO(GPIOH_5, 1, 25),
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CBUS_GPIO(GPIOH_6, 1, 26),
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CBUS_GPIO(GPIOH_7, 1, 27),
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CBUS_GPIO(GPIOH_8, 1, 28),
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CBUS_GPIO(GPIOH_9, 1, 29),
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/* BOOT */
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CBUS_GPIO(BOOT_0, 2, 0),
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CBUS_GPIO(BOOT_1, 2, 1),
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CBUS_GPIO(BOOT_2, 2, 2),
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CBUS_GPIO(BOOT_3, 2, 3),
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CBUS_GPIO(BOOT_4, 2, 4),
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CBUS_GPIO(BOOT_5, 2, 5),
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CBUS_GPIO(BOOT_6, 2, 6),
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CBUS_GPIO(BOOT_7, 2, 7),
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CBUS_GPIO(BOOT_8, 2, 8),
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CBUS_GPIO(BOOT_9, 2, 9),
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CBUS_GPIO(BOOT_10, 2, 10),
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CBUS_GPIO(BOOT_11, 2, 11),
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CBUS_GPIO(BOOT_12, 2, 12),
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CBUS_GPIO(BOOT_13, 2, 13),
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CBUS_GPIO(BOOT_14, 2, 14),
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CBUS_GPIO(BOOT_15, 2, 15),
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/* CARD */
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CBUS_GPIO(CARD_0, 2, 20),
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CBUS_GPIO(CARD_1, 2, 21),
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CBUS_GPIO(CARD_2, 2, 22),
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CBUS_GPIO(CARD_3, 2, 23),
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CBUS_GPIO(CARD_4, 2, 24),
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CBUS_GPIO(CARD_5, 2, 25),
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CBUS_GPIO(CARD_6, 2, 26),
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/* GPIOCLK */
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CBUS_GPIO(GPIOCLK_0, 3, 28),
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CBUS_GPIO(GPIOCLK_1, 3, 29),
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/* GPIOX */
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CBUS_GPIO(GPIOX_0, 4, 0),
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CBUS_GPIO(GPIOX_1, 4, 1),
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CBUS_GPIO(GPIOX_2, 4, 2),
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CBUS_GPIO(GPIOX_3, 4, 3),
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CBUS_GPIO(GPIOX_4, 4, 4),
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CBUS_GPIO(GPIOX_5, 4, 5),
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CBUS_GPIO(GPIOX_6, 4, 6),
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CBUS_GPIO(GPIOX_7, 4, 7),
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CBUS_GPIO(GPIOX_8, 4, 8),
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CBUS_GPIO(GPIOX_9, 4, 9),
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CBUS_GPIO(GPIOX_10, 4, 10),
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CBUS_GPIO(GPIOX_11, 4, 11),
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CBUS_GPIO(GPIOX_12, 4, 12),
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CBUS_GPIO(GPIOX_13, 4, 13),
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CBUS_GPIO(GPIOX_14, 4, 14),
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CBUS_GPIO(GPIOX_15, 4, 15),
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CBUS_GPIO(GPIOX_16, 4, 16),
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CBUS_GPIO(GPIOX_17, 4, 17),
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CBUS_GPIO(GPIOX_18, 4, 18),
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};
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#define AO_GPIO(_id, _bit) \
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[_id] = { \
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.id = (_id), \
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.name = __STRING(_id), \
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.oen = { \
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.type = MESON_PINCTRL_REGTYPE_GPIO, \
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.reg = 0, \
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.mask = __BIT(_bit) \
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}, \
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.out = { \
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.type = MESON_PINCTRL_REGTYPE_GPIO, \
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.reg = 0, \
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.mask = __BIT(_bit + 16) \
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}, \
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.in = { \
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.type = MESON_PINCTRL_REGTYPE_GPIO, \
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.reg = 4, \
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.mask = __BIT(_bit) \
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}, \
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.pupden = { \
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.type = MESON_PINCTRL_REGTYPE_PULL, \
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.reg = 0, \
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.mask = __BIT(_bit) \
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}, \
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.pupd = { \
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.type = MESON_PINCTRL_REGTYPE_PULL, \
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.reg = 0, \
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.mask = __BIT(_bit + 16) \
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}, \
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}
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static const struct meson_pinctrl_gpio mesongxl_aobus_gpios[] = {
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/* GPIOAO */
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AO_GPIO(GPIOAO_0, 0),
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AO_GPIO(GPIOAO_1, 1),
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AO_GPIO(GPIOAO_2, 2),
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AO_GPIO(GPIOAO_3, 3),
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AO_GPIO(GPIOAO_4, 4),
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AO_GPIO(GPIOAO_5, 5),
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AO_GPIO(GPIOAO_6, 6),
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AO_GPIO(GPIOAO_7, 7),
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AO_GPIO(GPIOAO_8, 8),
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AO_GPIO(GPIOAO_9, 9),
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};
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static const struct meson_pinctrl_group mesongxl_periphs_groups[] = {
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/* GPIOX */
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{ "sdio_d0", REG5, 31, { GPIOX_0 }, 1 },
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{ "sdio_d1", REG5, 30, { GPIOX_1 }, 1 },
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{ "sdio_d2", REG5, 29, { GPIOX_2 }, 1 },
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{ "sdio_d3", REG5, 28, { GPIOX_3 }, 1 },
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{ "sdio_clk", REG5, 27, { GPIOX_4 }, 1 },
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{ "sdio_cmd", REG5, 26, { GPIOX_5 }, 1 },
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{ "sdio_irq", REG5, 24, { GPIOX_7 }, 1 },
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{ "uart_tx_a", REG5, 19, { GPIOX_12 }, 1 },
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{ "uart_rx_a", REG5, 18, { GPIOX_13 }, 1 },
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{ "uart_cts_a", REG5, 17, { GPIOX_14 }, 1 },
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{ "uart_dts_a", REG5, 16, { GPIOX_15 }, 1 },
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{ "uart_tx_c", REG5, 13, { GPIOX_8 }, 1 },
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{ "uart_rx_c", REG5, 12, { GPIOX_9 }, 1 },
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{ "uart_cts_c", REG5, 11, { GPIOX_10 }, 1 },
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{ "uart_dts_c", REG5, 10, { GPIOX_11 }, 1 },
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{ "pwm_a", REG5, 25, { GPIOX_6 }, 1 },
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{ "pwm_e", REG5, 15, { GPIOX_16 }, 1 },
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{ "pwm_f_x", REG5, 14, { GPIOX_7 }, 1 },
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{ "spi_mosi", REG5, 3, { GPIOX_8 }, 1 },
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{ "spi_miso", REG5, 2, { GPIOX_9 }, 1 },
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{ "spi_ss0", REG5, 1, { GPIOX_10 }, 1 },
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{ "spi_sclk", REG5, 0, { GPIOX_11 }, 1 },
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/* GPIOZ */
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{ "eth_mdio", REG4, 23, { GPIOZ_0 }, 1 },
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{ "eth_mdc", REG4, 22, { GPIOZ_1 }, 1 },
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{ "eth_clk_rx_clk", REG4, 21, { GPIOZ_2 }, 1 },
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{ "eth_rx_dv", REG4, 20, { GPIOZ_3 }, 1 },
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{ "eth_rxd0", REG4, 19, { GPIOZ_4 }, 1 },
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{ "eth_rxd1", REG4, 18, { GPIOZ_5 }, 1 },
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{ "eth_rxd2", REG4, 17, { GPIOZ_6 }, 1 },
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{ "eth_rxd3", REG4, 16, { GPIOZ_7 }, 1 },
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{ "eth_rgmii_tx_clk", REG4, 15, { GPIOZ_8 }, 1 },
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{ "eth_tx_en", REG4, 14, { GPIOZ_9 }, 1 },
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{ "eth_txd0", REG4, 13, { GPIOZ_10 }, 1 },
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{ "eth_txd1", REG4, 12, { GPIOZ_11 }, 1 },
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{ "eth_txd2", REG4, 11, { GPIOZ_12 }, 1 },
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{ "eth_txd3", REG4, 10, { GPIOZ_13 }, 1 },
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{ "pwm_c", REG3, 20, { GPIOZ_15 }, 1 },
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{ "i2s_out_ch23_z", REG3, 26, { GPIOZ_5 }, 1 },
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{ "i2s_out_ch45_z", REG3, 25, { GPIOZ_6 }, 1 },
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{ "i2s_out_ch67_z", REG3, 24, { GPIOZ_7 }, 1 },
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{ "eth_link_led", REG4, 25, { GPIOZ_14 }, 1 },
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{ "eth_act_led", REG4, 24, { GPIOZ_15 }, 1 },
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/* GPIOH */
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{ "hdmi_hpd", REG6, 31, { GPIOH_0 }, 1 },
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{ "hdmi_sda", REG6, 30, { GPIOH_1 }, 1 },
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{ "hdmi_scl", REG6, 29, { GPIOH_2 }, 1 },
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{ "i2s_am_clk", REG6, 26, { GPIOH_6 }, 1 },
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{ "i2s_out_ao_clk", REG6, 25, { GPIOH_7 }, 1 },
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{ "i2s_out_lr_clk", REG6, 24, { GPIOH_8 }, 1 },
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{ "i2s_out_ch01", REG6, 23, { GPIOH_9 }, 1 },
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{ "spdif_out_h", REG6, 28, { GPIOH_4 }, 1 },
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/* GPIODV */
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{ "uart_tx_b", REG2, 16, { GPIODV_24 }, 1 },
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{ "uart_rx_b", REG2, 15, { GPIODV_25 }, 1 },
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{ "uart_cts_b", REG2, 14, { GPIODV_26 }, 1 },
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{ "uart_rts_b", REG2, 13, { GPIODV_27 }, 1 },
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{ "i2c_sda_c_dv18", REG1, 17, { GPIODV_18 }, 1 },
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{ "i2c_sck_c_dv19", REG1, 16, { GPIODV_19 }, 1 },
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{ "i2c_sda_a", REG1, 15, { GPIODV_24 }, 1 },
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{ "i2c_sck_a", REG1, 14, { GPIODV_25 }, 1 },
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{ "i2c_sda_b", REG1, 13, { GPIODV_26 }, 1 },
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{ "i2c_sck_b", REG1, 12, { GPIODV_27 }, 1 },
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{ "i2c_sda_c", REG1, 11, { GPIODV_28 }, 1 },
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{ "i2c_sck_c", REG1, 10, { GPIODV_29 }, 1 },
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{ "pwm_b", REG2, 11, { GPIODV_29 }, 1 },
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{ "pwm_d", REG2, 12, { GPIODV_28 }, 1 },
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{ "tsin_a_d0", REG2, 4, { GPIODV_0 }, 1 },
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{ "tsin_a_dp", REG2, 3, { GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, GPIODV_6, GPIODV_7 }, 7 },
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{ "tsin_a_clk", REG2, 2, { GPIODV_8 }, 1 },
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{ "tsin_a_sop", REG2, 1, { GPIODV_9 }, 1 },
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{ "tsin_a_d_valid", REG2, 0, { GPIODV_10 }, 1 },
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{ "tsin_a_fail", REG1, 31, { GPIODV_11 }, 1 },
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/* BOOT */
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{ "emmc_nand_d07", REG7, 31, { BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 }, 8 },
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{ "emmc_clk", REG7, 30, { BOOT_8 }, 1 },
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{ "emmc_cmd", REG7, 29, { BOOT_10 }, 1 },
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{ "emmc_ds", REG7, 28, { BOOT_15 }, 1 },
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{ "nor_d", REG7, 13, { BOOT_11 }, 1 },
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{ "nor_q", REG7, 12, { BOOT_12 }, 1 },
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{ "nor_c", REG7, 11, { BOOT_13 }, 1 },
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{ "nor_cs", REG7, 10, { BOOT_15 }, 1 },
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{ "nand_ce0", REG7, 7, { BOOT_8 }, 1 },
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{ "nand_ce1", REG7, 6, { BOOT_9 }, 1 },
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{ "nand_rb0", REG7, 5, { BOOT_10 }, 1 },
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{ "nand_ale", REG7, 4, { BOOT_11 }, 1 },
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{ "nand_cle", REG7, 3, { BOOT_12 }, 1 },
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{ "nand_wen_clk", REG7, 2, { BOOT_13 }, 1 },
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{ "nand_ren_wr", REG7, 1, { BOOT_14 }, 1 },
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{ "nand_dqs", REG7, 0, { BOOT_15 }, 1 },
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/* CARD */
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{ "sdcard_d1", REG6, 5, { CARD_0 }, 1 },
|
|
{ "sdcard_d0", REG6, 4, { CARD_1 }, 1 },
|
|
{ "sdcard_d3", REG6, 1, { CARD_4 }, 1 },
|
|
{ "sdcard_d2", REG6, 0, { CARD_5 }, 1 },
|
|
{ "sdcard_cmd", REG6, 2, { CARD_3 }, 1 },
|
|
{ "sdcard_clk", REG6, 3, { CARD_2 }, 1 },
|
|
|
|
/* GPIOCLK */
|
|
{ "pwm_f_clk", REG8, 30, { GPIOCLK_1 }, 1 },
|
|
};
|
|
|
|
static const struct meson_pinctrl_group mesongxl_aobus_groups[] = {
|
|
/* GPIOAO */
|
|
{ "uart_tx_ao_b_0", AOREG0, 26, { GPIOAO_0 }, 1 },
|
|
{ "uart_rx_ao_b_1", AOREG0, 25, { GPIOAO_1 }, 1 },
|
|
{ "uart_tx_ao_b", AOREG0, 24, { GPIOAO_4 }, 1 },
|
|
{ "uart_rx_ao_b", AOREG0, 23, { GPIOAO_5 }, 1 },
|
|
{ "uart_tx_ao_a", AOREG0, 12, { GPIOAO_0 }, 1 },
|
|
{ "uart_rx_ao_a", AOREG0, 11, { GPIOAO_1 }, 1 },
|
|
{ "uart_cts_ao_a", AOREG0, 10, { GPIOAO_2 }, 1 },
|
|
{ "uart_rts_ao_a", AOREG0, 9, { GPIOAO_3 }, 1 },
|
|
{ "uart_cts_ao_b", AOREG0, 8, { GPIOAO_2 }, 1 },
|
|
{ "uart_rts_ao_b", AOREG0, 7, { GPIOAO_3 }, 1 },
|
|
{ "i2c_sck_ao", AOREG0, 6, { GPIOAO_4 }, 1 },
|
|
{ "i2c_sda_ao", AOREG0, 5, { GPIOAO_5 }, 1 },
|
|
{ "i2c_slave_sck_ao", AOREG0, 2, { GPIOAO_4 }, 1 },
|
|
{ "i2c_slave_sda_ao", AOREG0, 1, { GPIOAO_5 }, 1 },
|
|
{ "remote_input_ao", AOREG0, 0, { GPIOAO_7 }, 1 },
|
|
{ "pwm_ao_a_3", AOREG0, 22, { GPIOAO_3 }, 1 },
|
|
{ "pwm_ao_b_6", AOREG0, 18, { GPIOAO_6 }, 1 },
|
|
{ "pwm_ao_a_8", AOREG0, 17, { GPIOAO_8 }, 1 },
|
|
{ "pwm_ao_b", AOREG0, 3, { GPIOAO_9 }, 1 },
|
|
{ "i2s_out_ch23_ao", AOREG1, 0, { GPIOAO_8 }, 1 },
|
|
{ "i2s_out_ch45_ao", AOREG1, 1, { GPIOAO_9 }, 1 },
|
|
{ "spdif_out_ao_6", AOREG0, 16, { GPIOAO_6 }, 1 },
|
|
{ "spdif_out_ao_9", AOREG0, 4, { GPIOAO_9 }, 1 },
|
|
{ "ao_cec", AOREG0, 15, { GPIOAO_8 }, 1 },
|
|
{ "ee_cec", AOREG0, 14, { GPIOAO_8 }, 1 },
|
|
|
|
/* TEST_N */
|
|
{ "i2s_out_ch67_ao", AOREG1, 2, { GPIO_TEST_N }, 1 },
|
|
|
|
};
|
|
|
|
const struct meson_pinctrl_config mesongxl_periphs_pinctrl_config = {
|
|
.name = "Meson GXL periphs GPIO",
|
|
.groups = mesongxl_periphs_groups,
|
|
.ngroups = __arraycount(mesongxl_periphs_groups),
|
|
.gpios = mesongxl_periphs_gpios,
|
|
.ngpios = __arraycount(mesongxl_periphs_gpios),
|
|
};
|
|
|
|
const struct meson_pinctrl_config mesongxl_aobus_pinctrl_config = {
|
|
.name = "Meson GXL AO GPIO",
|
|
.groups = mesongxl_aobus_groups,
|
|
.ngroups = __arraycount(mesongxl_aobus_groups),
|
|
.gpios = mesongxl_aobus_gpios,
|
|
.ngpios = __arraycount(mesongxl_aobus_gpios),
|
|
};
|