0b956d0b8b
counters. These counters do not exist on all CPUs, but where they do exist, can be used for counting events such as dcache misses that would otherwise be difficult or impossible to instrument by code inspection or hardware simulation. pmc(9) is meant to be a general interface. Initially, the Intel XScale counters are the only ones supported.
72 lines
3.0 KiB
C
72 lines
3.0 KiB
C
/* $NetBSD: xscalereg.h,v 1.2 2002/08/07 05:15:02 briggs Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_XSCALE_XSCALEREG_H_
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#define _ARM_XSCALE_XSCALEREG_H_
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/*
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* Register definitions for the Intel XScale processor core.
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*/
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/*
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* Performance Monitoring Unit (CP14)
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*
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* CP14.0 Performance Monitor Control Register
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* CP14.1 Clock Counter
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* CP14.2 Performance Counter Register 0
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* CP14.3 Performance Counter Register 1
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*/
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#define PMNC_E 0x00000001 /* enable counters */
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#define PMNC_P 0x00000002 /* reset both PMNs to 0 */
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#define PMNC_C 0x00000004 /* clock counter reset */
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#define PMNC_D 0x00000008 /* clock counter / 64 */
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#define PMNC_PMN0_IE 0x00000010 /* enable PMN0 interrupt */
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#define PMNC_PMN1_IE 0x00000020 /* enable PMN1 interrupt */
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#define PMNC_CC_IE 0x00000040 /* enable clock counter interrupt */
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#define PMNC_PMN0_IF 0x00000100 /* PMN0 overflow/interrupt */
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#define PMNC_PMN1_IF 0x00000200 /* PMN1 overflow/interrupt */
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#define PMNC_CC_IF 0x00000400 /* clock counter overflow/interrupt */
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#define PMNC_EVCNT0_MASK 0x000ff000 /* event to count for PMN0 */
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#define PMNC_EVCNT0_SHIFT 12
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#define PMNC_EVCNT1_MASK 0x0ff00000 /* event to count for PMN1 */
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#define PMNC_EVCNT1_SHIFT 20
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void xscale_pmu_init(void);
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#endif /* _ARM_XSCALE_XSCALEREG_H_ */
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