152 lines
3.9 KiB
C
152 lines
3.9 KiB
C
/* $NetBSD: if_ehreg.h,v 1.2 1996/03/08 16:24:51 mark Exp $ */
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/*
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* Copyright (c) 1995 Melvin Tang-Richardson.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by RiscBSD.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY RISCBSD ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL RISCBSD OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* if_ehreg.h
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*
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* Ether H register definitions.
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*/
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#define EH_RESET (0x18<<2)
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#define EH_DATA_PORT (0x10<<2)
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/* Special registers */
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#define EH_CONFIGA (0x0a<<2)
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/* Page 0 read registers */
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#define EH_COMMAND (0x00<<2)
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#define EH_CLAD0 (0x01<<2)
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#define EH_CLDA1 (0x02<<2)
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#define EH_BNRY (0x03<<2)
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#define EH_TSR (0x04<<2)
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#define EH_NCR (0x05<<2)
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#define EH_FIFO (0x06<<2)
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#define EH_ISR (0x07<<2)
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#define EH_CRDA0 (0x08<<2)
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#define EH_CRDA1 (0x09<<2)
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#define EH_RSR (0x0c<<2)
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/* Page 0 write registers */
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#define EH_PSTART (0x01<<2)
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#define EH_PSTOP (0x02<<2)
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#define EH_TPSR (0x04<<2)
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#define EH_TBCR0 (0x05<<2)
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#define EH_TBCR1 (0x06<<2)
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#define EH_RSAR0 (0x08<<2)
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#define EH_RSAR1 (0x09<<2)
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#define EH_RBCR0 (0x0a<<2)
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#define EH_RBCR1 (0x0b<<2)
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#define EH_RCR (0x0c<<2)
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#define EH_TCR (0x0d<<2)
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#define EH_DCR (0x0e<<2)
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#define EH_IMR (0x0f<<2)
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/* Page 1 write registers */
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#define EH_CURR (0x07<<2)
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/* Command bits */
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#define COM_STP (0x01)
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#define COM_STA (0x02)
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#define COM_TXP (0x04)
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#define COM_MASK_PAGE (0x3f)
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#define COM_READ (0x08)
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#define COM_WRITE (0x10)
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#define COM_SEND (0x18)
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#define COM_ABORT (0x20)
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#define COM_MASK_DMA (0xc7)
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#define COM_DMA_MASK (0x38)
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/* DCR bits */
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#define DCR_WTS (0x01)
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#define DCR_BOS (0x02)
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#define DCR_LAS (0x04)
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#define DCR_LS (0x08)
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#define DCR_ARM (0x10)
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/* TSR bits */
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#define TSR_PTX (0x01)
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#define TSR_COL (0x04)
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#define TSR_ABT (0x08)
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#define TSR_CRS (0x10)
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#define TSR_FU (0x20)
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#define TSR_CDH (0x40)
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#define TSR_OWC (0x80)
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#define TSR_DONE ((TSR_PTX)|(TSR_ABT))
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/* TCR bits */
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#define TCR_CRC (0x01)
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#define TCR_NORMALLOOP (0x00)
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#define TCR_NICMOD (0x02)
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#define TCR_ENDECMOD (0x04)
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#define TCR_EXTLOOP (0x06)
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#define TCR_ATD (0x08)
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#define TCR_OFST (0x10)
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/* ISR bits */
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#define ISR_PRX (0x01)
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#define ISR_PTX (0x02)
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#define ISR_RXE (0x04)
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#define ISR_TXE (0x08)
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#define ISR_OVW (0x10)
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#define ISR_CNT (0x20)
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#define ISR_RDC (0x40)
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#define ISR_RST (0x80)
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/* RSR bits */
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#define RSR_PRX (0x01)
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#define RSR_CRC (0x02)
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#define RSR_FAE (0x04)
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#define RSR_FO (0x08)
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#define RSR_MPA (0x10)
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#define RSR_PHY (0x20)
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#define RSR_DIS (0x40)
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#define RSR_DFR (0x80)
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struct eh_rxhdr {
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char rx_status;
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char rx_nxtpkt;
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char rx_rbc0;
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char rx_rbc1;
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};
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