455 lines
14 KiB
C
455 lines
14 KiB
C
/* $NetBSD: artsata.c,v 1.16 2007/07/19 21:53:15 dsl Exp $ */
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/*-
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* Copyright (c) 2003 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: artsata.c,v 1.16 2007/07/19 21:53:15 dsl Exp $");
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#include "opt_pciide.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/pci/pciide_i31244_reg.h>
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#include <dev/ata/satareg.h>
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#include <dev/ata/satavar.h>
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#include <dev/ata/atareg.h>
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#include <dev/ata/atavar.h>
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static void artisea_chip_map(struct pciide_softc*, struct pci_attach_args *);
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static int artsata_match(struct device *, struct cfdata *, void *);
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static void artsata_attach(struct device *, struct device *, void *);
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static const struct pciide_product_desc pciide_artsata_products[] = {
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{ PCI_PRODUCT_INTEL_31244,
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0,
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"Intel 31244 Serial ATA Controller",
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artisea_chip_map,
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},
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{ 0,
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0,
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NULL,
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NULL
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}
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};
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struct artisea_cmd_map
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{
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u_int8_t offset;
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u_int8_t size;
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};
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static const struct artisea_cmd_map artisea_dpa_cmd_map[] =
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{
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{ARTISEA_SUPDDR, 4}, /* 0 Data */
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{ARTISEA_SUPDER, 1}, /* 1 Error */
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{ARTISEA_SUPDCSR, 2}, /* 2 Sector Count */
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{ARTISEA_SUPDSNR, 2}, /* 3 Sector Number */
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{ARTISEA_SUPDCLR, 2}, /* 4 Cylinder Low */
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{ARTISEA_SUPDCHR, 2}, /* 5 Cylinder High */
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{ARTISEA_SUPDDHR, 1}, /* 6 Device/Head */
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{ARTISEA_SUPDCR, 1}, /* 7 Command */
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{ARTISEA_SUPDSR, 1}, /* 8 Status */
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{ARTISEA_SUPDFR, 2} /* 9 Feature */
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};
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#define ARTISEA_NUM_CHAN 4
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CFATTACH_DECL(artsata, sizeof(struct pciide_softc),
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artsata_match, artsata_attach, NULL, NULL);
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static int
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artsata_match(struct device *parent, struct cfdata *match,
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void *aux)
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{
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struct pci_attach_args *pa = aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_INTEL) {
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if (pciide_lookup_product(pa->pa_id, pciide_artsata_products))
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return (2);
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}
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return (0);
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}
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static void
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artsata_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pci_attach_args *pa = aux;
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struct pciide_softc *sc = (struct pciide_softc *)self;
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pciide_common_attach(sc, pa,
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pciide_lookup_product(pa->pa_id, pciide_artsata_products));
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}
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static void
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artisea_mapregs(struct pci_attach_args *pa, struct pciide_channel *cp,
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bus_size_t *cmdsizep, bus_size_t *ctlsizep,
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int (*pci_intr)(void *))
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{
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struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
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struct ata_channel *wdc_cp = &cp->ata_channel;
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struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
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const char *intrstr;
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pci_intr_handle_t intrhandle;
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int i;
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cp->compat = 0;
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if (sc->sc_pci_ih == NULL) {
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if (pci_intr_map(pa, &intrhandle) != 0) {
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aprint_error("%s: couldn't map native-PCI interrupt\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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goto bad;
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}
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intrstr = pci_intr_string(pa->pa_pc, intrhandle);
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sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
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intrhandle, IPL_BIO, pci_intr, sc);
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if (sc->sc_pci_ih != NULL) {
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aprint_normal("%s: using %s for native-PCI interrupt\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
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intrstr ? intrstr : "unknown interrupt");
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} else {
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aprint_error(
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"%s: couldn't establish native-PCI interrupt",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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if (intrstr != NULL)
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aprint_normal(" at %s", intrstr);
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aprint_normal("\n");
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goto bad;
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}
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}
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cp->ih = sc->sc_pci_ih;
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wdr->cmd_iot = sc->sc_ba5_st;
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if (bus_space_subregion (sc->sc_ba5_st, sc->sc_ba5_sh,
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ARTISEA_DPA_PORT_BASE(wdc_cp->ch_channel), 0x200,
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&wdr->cmd_baseioh) != 0) {
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aprint_error("%s: couldn't map %s channel cmd regs\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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goto bad;
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}
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wdr->ctl_iot = sc->sc_ba5_st;
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if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
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ARTISEA_SUPDDCTLR, 1, &cp->ctl_baseioh) != 0) {
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aprint_error("%s: couldn't map %s channel ctl regs\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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goto bad;
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}
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wdr->ctl_ioh = cp->ctl_baseioh;
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for (i = 0; i < WDC_NREG + 2; i++) {
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if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
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artisea_dpa_cmd_map[i].offset, artisea_dpa_cmd_map[i].size,
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&wdr->cmd_iohs[i]) != 0) {
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aprint_error("%s: couldn't subregion %s channel "
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"cmd regs\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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goto bad;
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}
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}
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wdr->data32iot = wdr->cmd_iot;
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wdr->data32ioh = wdr->cmd_iohs[0];
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wdr->sata_iot = wdr->cmd_iot;
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wdr->sata_baseioh = wdr->cmd_baseioh;
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if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
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ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSSR, 1,
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&wdr->sata_status) != 0) {
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aprint_error("%s: couldn't map channel %d "
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"sata_status regs\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
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wdc_cp->ch_channel);
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goto bad;
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}
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if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
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ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSER, 1,
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&wdr->sata_error) != 0) {
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aprint_error("%s: couldn't map channel %d "
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"sata_error regs\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
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wdc_cp->ch_channel);
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goto bad;
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}
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if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
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ARTISEA_SUPERSET_DPA_OFF + ARTISEA_SUPDSSCR, 1,
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&wdr->sata_control) != 0) {
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aprint_error("%s: couldn't map channel %d "
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"sata_control regs\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
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wdc_cp->ch_channel);
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goto bad;
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}
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wdcattach(wdc_cp);
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return;
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bad:
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wdc_cp->ch_flags |= ATACH_DISABLED;
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return;
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}
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static int
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artisea_chansetup(struct pciide_softc *sc, int channel,
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pcireg_t interface)
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{
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struct pciide_channel *cp = &sc->pciide_channels[channel];
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sc->wdc_chanarray[channel] = &cp->ata_channel;
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cp->name = PCIIDE_CHANNEL_NAME(channel);
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cp->ata_channel.ch_channel = channel;
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cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
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cp->ata_channel.ch_queue =
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malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
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cp->ata_channel.ch_ndrive = 2;
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if (cp->ata_channel.ch_queue == NULL) {
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aprint_error("%s %s channel: "
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"can't allocate memory for command queue",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
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return 0;
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}
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return 1;
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}
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static void
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artisea_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *pc;
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int chan;
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u_int32_t dma_ctl;
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u_int32_t cacheline_len;
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aprint_verbose("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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sc->sc_dma_ok = 1;
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/*
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* Errata #4 says that if the cacheline length is not set correctly,
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* we can get corrupt MWI and Memory-Block-Write transactions.
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*/
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cacheline_len = PCI_CACHELINE(pci_conf_read (pa->pa_pc, pa->pa_tag,
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PCI_BHLC_REG));
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if (cacheline_len == 0) {
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aprint_verbose(", but unused (cacheline size not set in PCI conf)\n");
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sc->sc_dma_ok = 0;
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return;
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}
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/*
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* Final step of the work-around is to force the DMA engine to use
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* the cache-line length information.
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*/
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dma_ctl = pci_conf_read(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR);
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dma_ctl |= SUDCSCR_DMA_WCAE | SUDCSCR_DMA_RCAE;
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pci_conf_write(pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUDCSCR, dma_ctl);
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sc->sc_wdcdev.dma_arg = sc;
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sc->sc_wdcdev.dma_init = pciide_dma_init;
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sc->sc_wdcdev.dma_start = pciide_dma_start;
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sc->sc_wdcdev.dma_finish = pciide_dma_finish;
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sc->sc_dma_iot = sc->sc_ba5_st;
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sc->sc_dmat = pa->pa_dmat;
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if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
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PCIIDE_OPTIONS_NODMA) {
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aprint_verbose(
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", but unused (forced off by config file)\n");
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sc->sc_dma_ok = 0;
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return;
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}
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/*
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* Set up the default handles for the DMA registers.
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* Just reserve 32 bits for each handle, unless space
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* doesn't permit it.
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*/
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for (chan = 0; chan < ARTISEA_NUM_CHAN; chan++) {
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pc = &sc->pciide_channels[chan];
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if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDCMDR, 2,
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&pc->dma_iohs[IDEDMA_CMD]) != 0 ||
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bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDSR, 1,
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&pc->dma_iohs[IDEDMA_CTL]) != 0 ||
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bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
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ARTISEA_DPA_PORT_BASE(chan) + ARTISEA_SUPDDDTPR, 4,
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&pc->dma_iohs[IDEDMA_TBL]) != 0) {
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sc->sc_dma_ok = 0;
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aprint_verbose(", but can't subregion registers\n");
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return;
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}
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}
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aprint_verbose("\n");
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}
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static void
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artisea_chip_map_dpa(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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bus_size_t cmdsize, ctlsize;
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pcireg_t interface;
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int channel;
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interface = PCI_INTERFACE(pa->pa_class);
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aprint_normal("%s: interface wired in DPA mode\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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if (pci_mapreg_map(pa, ARTISEA_PCI_DPA_BASE, PCI_MAPREG_MEM_TYPE_64BIT,
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0, &sc->sc_ba5_st, &sc->sc_ba5_sh, NULL, NULL) != 0)
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return;
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artisea_mapreg_dma(sc, pa);
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sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS;
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
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sc->sc_wdcdev.irqack = pciide_irqack;
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sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
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sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
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}
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sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
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sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
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sc->sc_wdcdev.sc_atac.atac_nchannels = ARTISEA_NUM_CHAN;
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sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
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wdc_allocate_regs(&sc->sc_wdcdev);
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/*
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* Perform a quick check to ensure that the device isn't configured
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* in Spread-spectrum clocking mode. This feature is buggy and has
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* been removed from the latest documentation.
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*
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* Note that although this bit is in the Channel regs, it's the same
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* for all channels, so we check it just once here.
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*/
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if ((bus_space_read_4 (sc->sc_ba5_st, sc->sc_ba5_sh,
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ARTISEA_DPA_PORT_BASE(0) + ARTISEA_SUPERSET_DPA_OFF +
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ARTISEA_SUPDPFR) & SUPDPFR_SSCEN) != 0) {
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aprint_error("%s: Spread-specturm clocking not supported by device\n",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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return;
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}
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/* Clear the LED0-only bit. */
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pci_conf_write (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0,
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pci_conf_read (pa->pa_pc, pa->pa_tag, ARTISEA_PCI_SUECSR0) &
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~SUECSR0_LED0_ONLY);
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for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
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channel++) {
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cp = &sc->pciide_channels[channel];
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if (artisea_chansetup(sc, channel, interface) == 0)
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continue;
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/* XXX We can probably do interrupts more efficiently. */
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artisea_mapregs(pa, cp, &cmdsize, &ctlsize, pciide_pci_intr);
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}
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}
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static void
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artisea_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
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{
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struct pciide_channel *cp;
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bus_size_t cmdsize, ctlsize;
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pcireg_t interface;
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int channel;
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if (pciide_chipen(sc, pa) == 0)
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return;
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interface = PCI_INTERFACE(pa->pa_class);
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if (interface == 0) {
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artisea_chip_map_dpa (sc, pa);
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return;
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}
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aprint_verbose("%s: bus-master DMA support present",
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sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
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#ifdef PCIIDE_I31244_DISABLEDMA
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if (sc->sc_pp->ide_product == PCI_PRODUCT_INTEL_31244 &&
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PCI_REVISION(pa->pa_class) == 0) {
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aprint_verbose(" but disabled due to rev. 0");
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sc->sc_dma_ok = 0;
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} else
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#endif
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pciide_mapreg_dma(sc, pa);
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aprint_verbose("\n");
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/*
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* XXX Configure LEDs to show activity.
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*/
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
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sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
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if (sc->sc_dma_ok) {
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sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
|
|
sc->sc_wdcdev.irqack = pciide_irqack;
|
|
sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
|
|
sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
|
|
}
|
|
sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
|
|
|
|
sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
|
|
sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
|
|
|
|
wdc_allocate_regs(&sc->sc_wdcdev);
|
|
|
|
for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
|
|
channel++) {
|
|
cp = &sc->pciide_channels[channel];
|
|
if (pciide_chansetup(sc, channel, interface) == 0)
|
|
continue;
|
|
pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize,
|
|
pciide_pci_intr);
|
|
}
|
|
}
|