127 lines
5.4 KiB
C
127 lines
5.4 KiB
C
/* $NetBSD: cmureg.h,v 1.4 2001/09/28 10:25:15 sato Exp $ */
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/*-
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* Copyright (c) 1999 SATO Kazumi. All rights reserved.
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* Copyright (c) 1999 PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the PocketBSD project
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* and its contributors.
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* 4. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* CMU (CLock MASK UNIT) Registers.
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* start 0x0B000060 (Vr4102-4111)
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* start 0x0F000060 (Vr4122-4131)
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* start 0x0A000004 (Vr4181)
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*/
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#define CMUNOMASK 0
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#define CMUCLKMASK 0x000 /* CMU Clock Mask Register */
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/* vr4102-4121 */
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#define VR4102_CMUMSKPCIU CMUNOMASK /* no PCICLK */
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#define VR4102_CMUMSKFFIR (1<<10) /* 1 supply 48MHz to FIR */
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#define VR4102_CMUMSKSHSP (1<<9) /* 1 supply 18.432MHz to HSP */
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#define VR4102_CMUMSKSSIU (1<<8) /* 1 supply 18.432MHz to SIU */
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#define VR4102_CMUMSKDSIU (1<<5) /* 1 supply Tclock to DSIU */
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#define VR4102_CMUMSKCSI CMUNOMASK /* no CSI clock */
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#define VR4102_CMUMSKFIR (1<<4) /* 1 supply Tclock to FIR */
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#define VR4102_CMUMSKKIU (1<<3) /* 1 supply Tclock to KIU */
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#define VR4102_CMUMSKAIU (1<<2) /* 1 supply Tclock to AIU */
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#define VR4102_CMUMSKSIU (1<<1) /* 1 supply Tclock to SIU */
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#define VR4102_CMUMSKPIU (1) /* 1 supply Tclock to PIU */
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/* vr4122-4131 */
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#define VR4122_CMUMSKPCIU ((1<<13)|(1<<7)) /* 1 supply PCICLK */
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#define VR4122_CMUMSKSCSI (1<<12) /* 1 supply CSI 18.432MHz clock */
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#define VR4122_CMUMSKDSIU (1<<11) /* 1 supply DSIU 18.432MHz clock */
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#define VR4122_CMUMSKFFIR (1<<10) /* 1 supply 48MHz to FIR */
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#define VR4122_CMUMSKSHSP CMUNOMASK /* no HSP */
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#define VR4122_CMUMSKSSIU (1<<8) /* 1 supply 18.432MHz to SIU */
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#define VR4122_CMUMSKCSI (1<<6) /* 1 supply Tclock to CSI */
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#define VR4122_CMUMSKFIR (1<<4) /* 1 supply Tclock to FIR */
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#define VR4122_CMUMSKKIU CMUNOMASK /* no KIU */
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#define VR4122_CMUMSKAIU CMUNOMASK /* no AIU */
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#define VR4122_CMUMSKSIU (1<<1) /* 1 supply Tclock to SIU */
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#define VR4122_CMUMSKPIU CMUNOMASK /* no PIU */
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/* vr4181 */
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#define VR4181_CMUMSKPCIU CMUNOMASK /* no PCICLK */
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#define VR4181_CMUMSKHSP CMUNOMASK /* no HSP */
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#define VR4181_CMUMSKDSIU CMUNOMASK /* no DSIU */
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#define VR4181_CMUMSKCSI (1<<6) /* 1 supply PCLK to CSI */
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#define VR4181_CMUMSKFIR CMUNOMASK /* no FIR */
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#define VR4181_CMUMSKKIU CMUNOMASK /* no KIU */
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#define VR4181_CMUMSKAIU (1<<5) /* 1 supply PLCK to AIU */
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#define VR4181_CMUMSKPIU (1<<4) /* 1 supply PLCK to PIU */
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#define VR4181_CMUMSKADU (1<<3) /* 1 supply PLCK to ADU */
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#define VR4181_CMUMSKSSIU (1<<2) /* 1 supply 18.432MHz to SIU */
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#define VR4181_CMUMSKSADU (1<<1) /* 1 supply 18.432MHz to ADU */
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#if defined SINGLE_VRIP_BASE
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#ifdef VRGROUP_4102_4121
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#define CMUMASK_PIU VR4102_CMUMSKPIU
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#define CMUMASK_SIU (VR4102_CMUMSKSIU|VR4102_CMUMSKSSIU)
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#define CMUMASK_AIU VR4102_CMUMSKAIU
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#define CMUMASK_KIU VR4102_CMUMSKKIU
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#define CMUMASK_FIR (VR4102_CMUMSKFIR|VR4102_CMUMSKFFIR)
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#define CMUMASK_DSIU VR4102_CMUMSKDSIU
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#define CMUMASK_HSP VR4102_CMUMSKHSP
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#define CMUMASK_CSI VR4102_CMUMSKCSI
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#define CMUMASK_PCIU VR4102_CMUMSKPCIU
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#endif /* VRGROUP_4102_4121 */
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#ifdef VRGROUP_4122_4131
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#define CMUMASK_PIU VR4122_CMUMSKPIU
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#define CMUMASK_SIU (VR4122_CMUMSKSIU|VR4122_CMUMSKSSIU)
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#define CMUMASK_AIU VR4122_CMUMSKAIU
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#define CMUMASK_KIU VR4122_CMUMSKKIU
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#define CMUMASK_FIR (VR4122_CMUMSKFIR|VR4122_CMUMSKFFIR)
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#define CMUMASK_DSIU VR4122_CMUMSKDSIU
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#define CMUMASK_HSP VR4122_CMUMSKHSP
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#define CMUMASK_CSI (VR4122_CMUMSKSCSI|VR4122_CMUMSKCSI)
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#define CMUMASK_PCIU VR4122_CMUMSKPCIU
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#endif /* VRGROUP_4122_4131 */
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#ifdef VRGROUP_4181
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#define CMUMASK_PIU VR4181_CMUMSKPIU
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#define CMUMASK_SIU VR4181_CMUMSKSSIU
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#define CMUMASK_AIU VR4181_CMUMSKAIU
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#define CMUMASK_KIU VR4181_CMUMSKKIU
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#define CMUMASK_FIR VR4181_CMUMSKFIR
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#define CMUMASK_DSIU VR4181_CMUMSKDSIU
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#define CMUMASK_HSP VR4181_CMUMSKHSP
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#define CMUMASK_CSI VR4181_CMUMSKCSI
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#define CMUMASK_PCIU VR4181_CMUMSKPCIU
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#endif /* VRGROUP_4181 */
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#endif /* SINGLE_VRIP_BASE */
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/* END cmureg.h */
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